forked from OSchip/llvm-project
142 lines
4.4 KiB
C++
142 lines
4.4 KiB
C++
//===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// The AMDGPUAsmPrinter is used to print both assembly string and also binary
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/// code. When passed an MCAsmStreamer it prints assembly and when passed
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/// an MCObjectStreamer it outputs binary code.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUAsmPrinter.h"
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#include "AMDGPU.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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using namespace llvm;
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static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
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MCStreamer &Streamer) {
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return new AMDGPUAsmPrinter(tm, Streamer);
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}
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extern "C" void LLVMInitializeR600AsmPrinter() {
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TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
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}
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/// We need to override this function so we can avoid
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/// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
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bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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if (STM.dumpCode()) {
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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MF.dump();
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#endif
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}
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SetupMachineFunction(MF);
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if (OutStreamer.hasRawTextSupport()) {
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OutStreamer.EmitRawText("@" + MF.getName() + ":");
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}
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OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
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if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
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EmitProgramInfo(MF);
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}
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EmitFunctionBody();
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return false;
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}
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void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
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unsigned MaxSGPR = 0;
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unsigned MaxVGPR = 0;
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bool VCCUsed = false;
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const SIRegisterInfo * RI =
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static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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unsigned numOperands = MI.getNumOperands();
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for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
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MachineOperand & MO = MI.getOperand(op_idx);
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unsigned maxUsed;
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unsigned width = 0;
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bool isSGPR = false;
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unsigned reg;
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unsigned hwReg;
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if (!MO.isReg()) {
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continue;
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}
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reg = MO.getReg();
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if (reg == AMDGPU::VCC) {
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VCCUsed = true;
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continue;
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}
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switch (reg) {
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default: break;
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case AMDGPU::EXEC:
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case AMDGPU::SI_LITERAL_CONSTANT:
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case AMDGPU::SREG_LIT_0:
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case AMDGPU::M0:
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continue;
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}
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if (AMDGPU::SReg_32RegClass.contains(reg)) {
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isSGPR = true;
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width = 1;
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} else if (AMDGPU::VReg_32RegClass.contains(reg)) {
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isSGPR = false;
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width = 1;
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} else if (AMDGPU::SReg_64RegClass.contains(reg)) {
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isSGPR = true;
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width = 2;
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} else if (AMDGPU::VReg_64RegClass.contains(reg)) {
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isSGPR = false;
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width = 2;
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} else if (AMDGPU::SReg_128RegClass.contains(reg)) {
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isSGPR = true;
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width = 4;
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} else if (AMDGPU::VReg_128RegClass.contains(reg)) {
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isSGPR = false;
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width = 4;
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} else if (AMDGPU::SReg_256RegClass.contains(reg)) {
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isSGPR = true;
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width = 8;
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} else {
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assert(!"Unknown register class");
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}
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hwReg = RI->getEncodingValue(reg);
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maxUsed = hwReg + width - 1;
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if (isSGPR) {
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MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
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} else {
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MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
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}
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}
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}
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}
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if (VCCUsed) {
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MaxSGPR += 2;
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}
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SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
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OutStreamer.EmitIntValue(MaxSGPR + 1, 4);
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OutStreamer.EmitIntValue(MaxVGPR + 1, 4);
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OutStreamer.EmitIntValue(MFI->SPIPSInputAddr, 4);
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}
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