forked from OSchip/llvm-project
359 lines
11 KiB
C++
359 lines
11 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -O1 -disable-llvm-passes -emit-llvm %s -o - -triple=x86_64-linux-gnu | FileCheck %s
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extern volatile int i;
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// CHECK-LABEL: @_Z8OneCaseLv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2:![0-9]+]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !6
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void OneCaseL() {
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switch (i) {
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[[likely]] case 1: break;
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}
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}
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// CHECK-LABEL: @_Z8OneCaseUv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_BB:%.*]]
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// CHECK-NEXT: ], !prof !7
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// CHECK: sw.bb:
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// CHECK-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
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// CHECK-NEXT: store volatile i32 [[INC]], i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void OneCaseU() {
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switch (i) {
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[[unlikely]] case 1: ++i; break;
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}
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}
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// CHECK-LABEL: @_Z10TwoCasesLNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG]]
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// CHECK-NEXT: i32 2, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !8
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void TwoCasesLN() {
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switch (i) {
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[[likely]] case 1: break;
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case 2: break;
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}
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}
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// CHECK-LABEL: @_Z10TwoCasesUNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG]]
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// CHECK-NEXT: i32 2, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !9
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void TwoCasesUN() {
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switch (i) {
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[[unlikely]] case 1: break;
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case 2: break;
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}
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}
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// CHECK-LABEL: @_Z10TwoCasesLUv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG]]
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// CHECK-NEXT: i32 2, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !10
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void TwoCasesLU() {
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switch (i) {
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[[likely]] case 1: break;
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[[unlikely]] case 2: break;
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}
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}
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// CHECK-LABEL: @_Z20CasesFallthroughNNLNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_BB:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_BB]]
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// CHECK-NEXT: i32 3, label [[SW_BB1:%.*]]
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// CHECK-NEXT: i32 4, label [[SW_BB1]]
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// CHECK-NEXT: ], !prof !11
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// CHECK: sw.bb:
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// CHECK-NEXT: br label [[SW_BB1]]
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// CHECK: sw.bb1:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void CasesFallthroughNNLN() {
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switch (i) {
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case 1:
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case 2:
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[[likely]] case 3:
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case 4: break;
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}
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}
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// CHECK-LABEL: @_Z20CasesFallthroughNNUNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_BB:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_BB]]
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// CHECK-NEXT: i32 3, label [[SW_BB1:%.*]]
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// CHECK-NEXT: i32 4, label [[SW_BB1]]
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// CHECK-NEXT: ], !prof !12
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// CHECK: sw.bb:
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// CHECK-NEXT: br label [[SW_BB1]]
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// CHECK: sw.bb1:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void CasesFallthroughNNUN() {
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switch (i) {
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case 1:
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case 2:
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[[unlikely]] case 3:
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case 4: break;
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}
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}
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// CHECK-LABEL: @_Z28CasesFallthroughRangeSmallLNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_BB:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_BB]]
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// CHECK-NEXT: i32 3, label [[SW_BB]]
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// CHECK-NEXT: i32 4, label [[SW_BB]]
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// CHECK-NEXT: i32 5, label [[SW_BB]]
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// CHECK-NEXT: i32 102, label [[SW_BB1:%.*]]
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// CHECK-NEXT: i32 103, label [[SW_BB2:%.*]]
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// CHECK-NEXT: i32 104, label [[SW_BB2]]
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// CHECK-NEXT: ], !prof !13
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// CHECK: sw.bb:
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// CHECK-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
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// CHECK-NEXT: store volatile i32 [[INC]], i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: br label [[SW_BB1]]
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// CHECK: sw.bb1:
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// CHECK-NEXT: br label [[SW_BB2]]
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// CHECK: sw.bb2:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void CasesFallthroughRangeSmallLN() {
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switch (i) {
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case 1 ... 5: ++i;
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case 102:
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[[likely]] case 103:
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case 104: break;
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}
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}
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// CHECK-LABEL: @_Z28CasesFallthroughRangeSmallUNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_BB:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_BB]]
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// CHECK-NEXT: i32 3, label [[SW_BB]]
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// CHECK-NEXT: i32 4, label [[SW_BB]]
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// CHECK-NEXT: i32 5, label [[SW_BB]]
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// CHECK-NEXT: i32 102, label [[SW_BB1:%.*]]
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// CHECK-NEXT: i32 103, label [[SW_BB2:%.*]]
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// CHECK-NEXT: i32 104, label [[SW_BB2]]
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// CHECK-NEXT: ], !prof !14
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// CHECK: sw.bb:
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// CHECK-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
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// CHECK-NEXT: store volatile i32 [[INC]], i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: br label [[SW_BB1]]
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// CHECK: sw.bb1:
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// CHECK-NEXT: br label [[SW_BB2]]
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// CHECK: sw.bb2:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void CasesFallthroughRangeSmallUN() {
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switch (i) {
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case 1 ... 5: ++i;
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case 102:
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[[unlikely]] case 103:
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case 104: break;
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}
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}
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// CHECK-LABEL: @_Z29CasesFallthroughRangeLargeLLNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_CASERANGE:%.*]] [
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// CHECK-NEXT: i32 1003, label [[SW_BB1:%.*]]
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// CHECK-NEXT: i32 104, label [[SW_BB1]]
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// CHECK-NEXT: ], !prof !8
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// CHECK: sw.bb:
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// CHECK-NEXT: br label [[SW_BB1]]
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// CHECK: sw.bb1:
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// CHECK-NEXT: br label [[SW_EPILOG:%.*]]
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// CHECK: sw.caserange:
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// CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 0
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// CHECK-NEXT: [[INBOUNDS:%.*]] = icmp ule i32 [[TMP1]], 64
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// CHECK-NEXT: [[INBOUNDS_EXPVAL:%.*]] = call i1 @llvm.expect.i1(i1 [[INBOUNDS]], i1 true)
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// CHECK-NEXT: br i1 [[INBOUNDS_EXPVAL]], label [[SW_BB:%.*]], label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void CasesFallthroughRangeLargeLLN() {
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switch (i) {
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[[likely]] case 0 ... 64:
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[[likely]] case 1003:
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case 104: break;
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}
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}
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// CHECK-LABEL: @_Z29CasesFallthroughRangeLargeUUNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_CASERANGE:%.*]] [
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// CHECK-NEXT: i32 1003, label [[SW_BB1:%.*]]
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// CHECK-NEXT: i32 104, label [[SW_BB1]]
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// CHECK-NEXT: ], !prof !9
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// CHECK: sw.bb:
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// CHECK-NEXT: br label [[SW_BB1]]
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// CHECK: sw.bb1:
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// CHECK-NEXT: br label [[SW_EPILOG:%.*]]
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// CHECK: sw.caserange:
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// CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 0
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// CHECK-NEXT: [[INBOUNDS:%.*]] = icmp ule i32 [[TMP1]], 64
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// CHECK-NEXT: [[INBOUNDS_EXPVAL:%.*]] = call i1 @llvm.expect.i1(i1 [[INBOUNDS]], i1 false)
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// CHECK-NEXT: br i1 [[INBOUNDS_EXPVAL]], label [[SW_BB:%.*]], label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void CasesFallthroughRangeLargeUUN() {
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switch (i) {
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[[unlikely]] case 0 ... 64:
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[[unlikely]] case 1003:
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case 104: break;
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}
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}
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// CHECK-LABEL: @_Z15OneCaseDefaultLv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG:%.*]]
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// CHECK-NEXT: ], !prof !15
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// CHECK: sw.default:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void OneCaseDefaultL() {
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switch (i) {
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case 1: break;
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[[likely]] default: break;
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}
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}
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// CHECK-LABEL: @_Z15OneCaseDefaultUv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG:%.*]]
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// CHECK-NEXT: ], !prof !16
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// CHECK: sw.default:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void OneCaseDefaultU() {
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switch (i) {
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case 1: break;
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[[unlikely]] default: break;
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}
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}
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// CHECK-LABEL: @_Z18TwoCasesDefaultLNLv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !17
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// CHECK: sw.default:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void TwoCasesDefaultLNL() {
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switch (i) {
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[[likely]] case 1: break;
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case 2: break;
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[[likely]] default: break;
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}
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}
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// CHECK-LABEL: @_Z18TwoCasesDefaultLNNv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !8
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// CHECK: sw.default:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void TwoCasesDefaultLNN() {
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switch (i) {
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[[likely]] case 1: break;
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case 2: break;
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default: break;
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}
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}
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// CHECK-LABEL: @_Z18TwoCasesDefaultLNUv(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @i, align 4, !tbaa [[TBAA2]]
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// CHECK-NEXT: switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
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// CHECK-NEXT: i32 1, label [[SW_EPILOG:%.*]]
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// CHECK-NEXT: i32 2, label [[SW_EPILOG]]
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// CHECK-NEXT: ], !prof !18
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// CHECK: sw.default:
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// CHECK-NEXT: br label [[SW_EPILOG]]
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// CHECK: sw.epilog:
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// CHECK-NEXT: ret void
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//
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void TwoCasesDefaultLNU() {
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switch (i) {
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[[likely]] case 1: break;
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case 2: break;
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[[unlikely]] default: break;
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}
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}
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