forked from OSchip/llvm-project
547 lines
14 KiB
C++
547 lines
14 KiB
C++
//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that NVPTX uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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#include "NVPTX.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace NVPTXISD {
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enum NodeType : unsigned {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper,
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CALL,
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RET_FLAG,
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LOAD_PARAM,
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DeclareParam,
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DeclareScalarParam,
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DeclareRetParam,
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DeclareRet,
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DeclareScalarRet,
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PrintCall,
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PrintConvergentCall,
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PrintCallUni,
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PrintConvergentCallUni,
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CallArgBegin,
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CallArg,
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LastCallArg,
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CallArgEnd,
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CallVoid,
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CallVal,
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CallSymbol,
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Prototype,
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MoveParam,
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PseudoUseParam,
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RETURN,
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CallSeqBegin,
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CallSeqEnd,
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CallPrototype,
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FUN_SHFL_CLAMP,
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FUN_SHFR_CLAMP,
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MUL_WIDE_SIGNED,
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MUL_WIDE_UNSIGNED,
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IMAD,
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Dummy,
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LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LoadV4,
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LDGV2, // LDG.v2
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LDGV4, // LDG.v4
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LDUV2, // LDU.v2
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LDUV4, // LDU.v4
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StoreV2,
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StoreV4,
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LoadParam,
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LoadParamV2,
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LoadParamV4,
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StoreParam,
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StoreParamV2,
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StoreParamV4,
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StoreParamS32, // to sext and store a <32bit value, not used currently
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StoreParamU32, // to zext and store a <32bit value, not used currently
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StoreRetval,
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StoreRetvalV2,
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StoreRetvalV4,
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// Texture intrinsics
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Tex1DFloatS32,
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Tex1DFloatFloat,
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Tex1DFloatFloatLevel,
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Tex1DFloatFloatGrad,
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Tex1DS32S32,
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Tex1DS32Float,
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Tex1DS32FloatLevel,
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Tex1DS32FloatGrad,
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Tex1DU32S32,
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Tex1DU32Float,
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Tex1DU32FloatLevel,
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Tex1DU32FloatGrad,
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Tex1DArrayFloatS32,
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Tex1DArrayFloatFloat,
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Tex1DArrayFloatFloatLevel,
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Tex1DArrayFloatFloatGrad,
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Tex1DArrayS32S32,
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Tex1DArrayS32Float,
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Tex1DArrayS32FloatLevel,
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Tex1DArrayS32FloatGrad,
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Tex1DArrayU32S32,
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Tex1DArrayU32Float,
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Tex1DArrayU32FloatLevel,
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Tex1DArrayU32FloatGrad,
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Tex2DFloatS32,
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Tex2DFloatFloat,
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Tex2DFloatFloatLevel,
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Tex2DFloatFloatGrad,
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Tex2DS32S32,
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Tex2DS32Float,
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Tex2DS32FloatLevel,
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Tex2DS32FloatGrad,
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Tex2DU32S32,
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Tex2DU32Float,
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Tex2DU32FloatLevel,
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Tex2DU32FloatGrad,
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Tex2DArrayFloatS32,
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Tex2DArrayFloatFloat,
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Tex2DArrayFloatFloatLevel,
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Tex2DArrayFloatFloatGrad,
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Tex2DArrayS32S32,
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Tex2DArrayS32Float,
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Tex2DArrayS32FloatLevel,
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Tex2DArrayS32FloatGrad,
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Tex2DArrayU32S32,
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Tex2DArrayU32Float,
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Tex2DArrayU32FloatLevel,
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Tex2DArrayU32FloatGrad,
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Tex3DFloatS32,
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Tex3DFloatFloat,
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Tex3DFloatFloatLevel,
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Tex3DFloatFloatGrad,
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Tex3DS32S32,
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Tex3DS32Float,
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Tex3DS32FloatLevel,
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Tex3DS32FloatGrad,
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Tex3DU32S32,
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Tex3DU32Float,
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Tex3DU32FloatLevel,
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Tex3DU32FloatGrad,
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TexCubeFloatFloat,
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TexCubeFloatFloatLevel,
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TexCubeS32Float,
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TexCubeS32FloatLevel,
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TexCubeU32Float,
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TexCubeU32FloatLevel,
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TexCubeArrayFloatFloat,
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TexCubeArrayFloatFloatLevel,
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TexCubeArrayS32Float,
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TexCubeArrayS32FloatLevel,
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TexCubeArrayU32Float,
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TexCubeArrayU32FloatLevel,
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Tld4R2DFloatFloat,
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Tld4G2DFloatFloat,
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Tld4B2DFloatFloat,
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Tld4A2DFloatFloat,
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Tld4R2DS64Float,
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Tld4G2DS64Float,
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Tld4B2DS64Float,
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Tld4A2DS64Float,
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Tld4R2DU64Float,
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Tld4G2DU64Float,
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Tld4B2DU64Float,
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Tld4A2DU64Float,
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TexUnified1DFloatS32,
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TexUnified1DFloatFloat,
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TexUnified1DFloatFloatLevel,
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TexUnified1DFloatFloatGrad,
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TexUnified1DS32S32,
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TexUnified1DS32Float,
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TexUnified1DS32FloatLevel,
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TexUnified1DS32FloatGrad,
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TexUnified1DU32S32,
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TexUnified1DU32Float,
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TexUnified1DU32FloatLevel,
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TexUnified1DU32FloatGrad,
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TexUnified1DArrayFloatS32,
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TexUnified1DArrayFloatFloat,
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TexUnified1DArrayFloatFloatLevel,
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TexUnified1DArrayFloatFloatGrad,
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TexUnified1DArrayS32S32,
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TexUnified1DArrayS32Float,
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TexUnified1DArrayS32FloatLevel,
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TexUnified1DArrayS32FloatGrad,
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TexUnified1DArrayU32S32,
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TexUnified1DArrayU32Float,
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TexUnified1DArrayU32FloatLevel,
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TexUnified1DArrayU32FloatGrad,
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TexUnified2DFloatS32,
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TexUnified2DFloatFloat,
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TexUnified2DFloatFloatLevel,
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TexUnified2DFloatFloatGrad,
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TexUnified2DS32S32,
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TexUnified2DS32Float,
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TexUnified2DS32FloatLevel,
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TexUnified2DS32FloatGrad,
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TexUnified2DU32S32,
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TexUnified2DU32Float,
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TexUnified2DU32FloatLevel,
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TexUnified2DU32FloatGrad,
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TexUnified2DArrayFloatS32,
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TexUnified2DArrayFloatFloat,
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TexUnified2DArrayFloatFloatLevel,
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TexUnified2DArrayFloatFloatGrad,
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TexUnified2DArrayS32S32,
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TexUnified2DArrayS32Float,
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TexUnified2DArrayS32FloatLevel,
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TexUnified2DArrayS32FloatGrad,
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TexUnified2DArrayU32S32,
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TexUnified2DArrayU32Float,
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TexUnified2DArrayU32FloatLevel,
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TexUnified2DArrayU32FloatGrad,
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TexUnified3DFloatS32,
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TexUnified3DFloatFloat,
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TexUnified3DFloatFloatLevel,
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TexUnified3DFloatFloatGrad,
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TexUnified3DS32S32,
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TexUnified3DS32Float,
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TexUnified3DS32FloatLevel,
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TexUnified3DS32FloatGrad,
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TexUnified3DU32S32,
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TexUnified3DU32Float,
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TexUnified3DU32FloatLevel,
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TexUnified3DU32FloatGrad,
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TexUnifiedCubeFloatFloat,
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TexUnifiedCubeFloatFloatLevel,
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TexUnifiedCubeS32Float,
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TexUnifiedCubeS32FloatLevel,
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TexUnifiedCubeU32Float,
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TexUnifiedCubeU32FloatLevel,
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TexUnifiedCubeArrayFloatFloat,
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TexUnifiedCubeArrayFloatFloatLevel,
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TexUnifiedCubeArrayS32Float,
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TexUnifiedCubeArrayS32FloatLevel,
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TexUnifiedCubeArrayU32Float,
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TexUnifiedCubeArrayU32FloatLevel,
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Tld4UnifiedR2DFloatFloat,
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Tld4UnifiedG2DFloatFloat,
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Tld4UnifiedB2DFloatFloat,
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Tld4UnifiedA2DFloatFloat,
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Tld4UnifiedR2DS64Float,
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Tld4UnifiedG2DS64Float,
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Tld4UnifiedB2DS64Float,
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Tld4UnifiedA2DS64Float,
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Tld4UnifiedR2DU64Float,
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Tld4UnifiedG2DU64Float,
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Tld4UnifiedB2DU64Float,
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Tld4UnifiedA2DU64Float,
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// Surface intrinsics
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Suld1DI8Clamp,
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Suld1DI16Clamp,
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Suld1DI32Clamp,
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Suld1DI64Clamp,
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Suld1DV2I8Clamp,
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Suld1DV2I16Clamp,
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Suld1DV2I32Clamp,
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Suld1DV2I64Clamp,
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Suld1DV4I8Clamp,
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Suld1DV4I16Clamp,
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Suld1DV4I32Clamp,
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Suld1DArrayI8Clamp,
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Suld1DArrayI16Clamp,
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Suld1DArrayI32Clamp,
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Suld1DArrayI64Clamp,
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Suld1DArrayV2I8Clamp,
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Suld1DArrayV2I16Clamp,
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Suld1DArrayV2I32Clamp,
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Suld1DArrayV2I64Clamp,
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Suld1DArrayV4I8Clamp,
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Suld1DArrayV4I16Clamp,
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Suld1DArrayV4I32Clamp,
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Suld2DI8Clamp,
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Suld2DI16Clamp,
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Suld2DI32Clamp,
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Suld2DI64Clamp,
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Suld2DV2I8Clamp,
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Suld2DV2I16Clamp,
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Suld2DV2I32Clamp,
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Suld2DV2I64Clamp,
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Suld2DV4I8Clamp,
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Suld2DV4I16Clamp,
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Suld2DV4I32Clamp,
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Suld2DArrayI8Clamp,
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Suld2DArrayI16Clamp,
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Suld2DArrayI32Clamp,
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Suld2DArrayI64Clamp,
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Suld2DArrayV2I8Clamp,
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Suld2DArrayV2I16Clamp,
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Suld2DArrayV2I32Clamp,
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Suld2DArrayV2I64Clamp,
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Suld2DArrayV4I8Clamp,
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Suld2DArrayV4I16Clamp,
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Suld2DArrayV4I32Clamp,
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Suld3DI8Clamp,
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Suld3DI16Clamp,
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Suld3DI32Clamp,
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Suld3DI64Clamp,
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Suld3DV2I8Clamp,
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Suld3DV2I16Clamp,
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Suld3DV2I32Clamp,
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Suld3DV2I64Clamp,
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Suld3DV4I8Clamp,
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Suld3DV4I16Clamp,
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Suld3DV4I32Clamp,
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Suld1DI8Trap,
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Suld1DI16Trap,
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Suld1DI32Trap,
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Suld1DI64Trap,
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Suld1DV2I8Trap,
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Suld1DV2I16Trap,
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Suld1DV2I32Trap,
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Suld1DV2I64Trap,
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Suld1DV4I8Trap,
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Suld1DV4I16Trap,
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Suld1DV4I32Trap,
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Suld1DArrayI8Trap,
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Suld1DArrayI16Trap,
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Suld1DArrayI32Trap,
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Suld1DArrayI64Trap,
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Suld1DArrayV2I8Trap,
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Suld1DArrayV2I16Trap,
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Suld1DArrayV2I32Trap,
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Suld1DArrayV2I64Trap,
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Suld1DArrayV4I8Trap,
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Suld1DArrayV4I16Trap,
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Suld1DArrayV4I32Trap,
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Suld2DI8Trap,
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Suld2DI16Trap,
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Suld2DI32Trap,
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Suld2DI64Trap,
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Suld2DV2I8Trap,
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Suld2DV2I16Trap,
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Suld2DV2I32Trap,
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Suld2DV2I64Trap,
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Suld2DV4I8Trap,
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Suld2DV4I16Trap,
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Suld2DV4I32Trap,
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Suld2DArrayI8Trap,
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Suld2DArrayI16Trap,
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Suld2DArrayI32Trap,
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Suld2DArrayI64Trap,
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Suld2DArrayV2I8Trap,
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Suld2DArrayV2I16Trap,
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Suld2DArrayV2I32Trap,
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Suld2DArrayV2I64Trap,
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Suld2DArrayV4I8Trap,
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Suld2DArrayV4I16Trap,
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Suld2DArrayV4I32Trap,
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Suld3DI8Trap,
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Suld3DI16Trap,
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Suld3DI32Trap,
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Suld3DI64Trap,
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Suld3DV2I8Trap,
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Suld3DV2I16Trap,
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Suld3DV2I32Trap,
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Suld3DV2I64Trap,
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Suld3DV4I8Trap,
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Suld3DV4I16Trap,
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Suld3DV4I32Trap,
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Suld1DI8Zero,
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Suld1DI16Zero,
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Suld1DI32Zero,
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Suld1DI64Zero,
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Suld1DV2I8Zero,
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Suld1DV2I16Zero,
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Suld1DV2I32Zero,
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Suld1DV2I64Zero,
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Suld1DV4I8Zero,
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Suld1DV4I16Zero,
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Suld1DV4I32Zero,
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Suld1DArrayI8Zero,
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Suld1DArrayI16Zero,
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Suld1DArrayI32Zero,
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Suld1DArrayI64Zero,
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Suld1DArrayV2I8Zero,
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Suld1DArrayV2I16Zero,
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Suld1DArrayV2I32Zero,
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Suld1DArrayV2I64Zero,
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Suld1DArrayV4I8Zero,
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Suld1DArrayV4I16Zero,
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Suld1DArrayV4I32Zero,
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Suld2DI8Zero,
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Suld2DI16Zero,
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Suld2DI32Zero,
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Suld2DI64Zero,
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Suld2DV2I8Zero,
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Suld2DV2I16Zero,
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Suld2DV2I32Zero,
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Suld2DV2I64Zero,
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Suld2DV4I8Zero,
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Suld2DV4I16Zero,
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Suld2DV4I32Zero,
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Suld2DArrayI8Zero,
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Suld2DArrayI16Zero,
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Suld2DArrayI32Zero,
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Suld2DArrayI64Zero,
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Suld2DArrayV2I8Zero,
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Suld2DArrayV2I16Zero,
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Suld2DArrayV2I32Zero,
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Suld2DArrayV2I64Zero,
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Suld2DArrayV4I8Zero,
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Suld2DArrayV4I16Zero,
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Suld2DArrayV4I32Zero,
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Suld3DI8Zero,
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Suld3DI16Zero,
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Suld3DI32Zero,
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Suld3DI64Zero,
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Suld3DV2I8Zero,
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Suld3DV2I16Zero,
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Suld3DV2I32Zero,
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Suld3DV2I64Zero,
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Suld3DV4I8Zero,
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Suld3DV4I16Zero,
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Suld3DV4I32Zero
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};
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}
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class NVPTXSubtarget;
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class NVPTXTargetLowering : public TargetLowering {
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public:
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explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
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const NVPTXSubtarget &STI);
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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const char *getTargetNodeName(unsigned Opcode) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type
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/// Used to guide target specific optimizations, like loop strength
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/// reduction (LoopStrengthReduce.cpp) and memory optimization for
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/// address mode (CodeGenPrepare.cpp)
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS) const override;
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bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
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// Truncating 64-bit to 32-bit is free in SASS.
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if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
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return false;
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return SrcTy->getPrimitiveSizeInBits() == 64 &&
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DstTy->getPrimitiveSizeInBits() == 32;
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}
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
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EVT VT) const override {
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if (VT.isVector())
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return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
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return MVT::i1;
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}
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ConstraintType getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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SDValue LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
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const SmallVectorImpl<ISD::OutputArg> &,
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unsigned retAlignment,
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const ImmutableCallSite *CS) const;
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SDValue
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LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
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SelectionDAG &DAG) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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const NVPTXTargetMachine *nvTM;
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// PTX always uses 32-bit shift amounts
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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return MVT::i32;
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}
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(EVT VT) const override;
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bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
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bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
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bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
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private:
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const NVPTXSubtarget &STI; // cache the subtarget here
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SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
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Type *Ty, unsigned Idx) const;
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};
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} // namespace llvm
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#endif
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