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llvm-project/llvm/test
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Jay Foad fc7e3e7dd9 [AMDGPU] Set SchedRW on real instructions 
Coyp SchedRW from pseudos to real instructions so that llvm-mca has
access to it. This is NFC for normal compiler codegen, which schedules
pseudos not real instructions.

Add an llvm-mca test for some high latency double-precision instructions
as a smoke test.

Differential Revision: https://reviews.llvm.org/D99187
 		2021-03-23 15:38:11 +00:00
..
Analysis [IR][SVE] Add new llvm.experimental.stepvector intrinsic 2021-03-23 10:43:35 +00:00
Assembler [Assembler] Fix global icmp test 2021-03-08 17:26:49 +01:00
Bindings [OCaml] Add (get/set)_module_identifer functions 2021-03-20 20:41:51 +05:30
Bitcode [IR] Add vscale_range IR function attribute 2021-03-22 12:05:06 +00:00
BugPoint
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CodeGen [RISCV] Further optimize BUILD_VECTORs with repeated elements 2021-03-23 14:14:48 +00:00
DebugInfo [llvm-symbolizer][llvm-nm] Fix AArch64 and ARM mapping symbols handling. 2021-03-23 14:17:12 +01:00
Demangle
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Examples
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ExecutionEngine Temporarily revert "[lli] Make -jit-kind=orc the default JIT engine" 2021-03-23 12:01:30 +01:00
Feature
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FileCheck [FileCheck] Fix redundant diagnostics due to numeric errors 2021-03-17 19:25:41 -04:00
Instrumentation [SanitizerCoverage] Use External on Windows 2021-03-22 23:05:36 -07:00
Integer Temporarily revert "[lli] Make -jit-kind=orc the default JIT engine" 2021-03-23 12:01:30 +01:00
JitListener
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LTO [LTO][MC] Discard non-prevailing defined symbols in module-level assembly 2021-03-18 15:33:42 -07:00
Linker Support intrinsic overloading on unnamed types 2021-03-19 14:34:25 +01:00
MC AMDGPU: Fix allowing immediates for tail call pseudo. 2021-03-21 13:14:04 -04:00
MachineVerifier [GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes) 2021-03-19 14:37:19 -07:00
Object
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ObjectYAML [WebAssembly][yaml2obj][obj2yaml] Elem sections for nonzero tables 2021-03-05 11:45:15 +01:00
Other Revert "A new option -print-on-crash that prints the IR as it was upon entering the last pass when there is a crash." 2021-03-23 10:09:27 -04:00
Reduce
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SafepointIRVerifier
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Support
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SymbolRewriter
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TableGen [openacc][openmp] Reduce number of generated file and prefer inclusion of .inc 2021-03-23 09:16:53 -04:00
ThinLTO/X86 [llvm] Change DSOLocalEquivalent type if the underlying global value type changes 2021-03-09 15:09:48 -08:00
Transforms [PhaseOrdering] add AVX attribute to make test less fragile; NFC 2021-03-23 11:34:33 -04:00
Unit [lit] Sort test start times based on prior test timing data 2021-03-16 05:23:04 -04:00
Verifier [IR][SVE] Add new llvm.experimental.stepvector intrinsic 2021-03-23 10:43:35 +00:00
YAMLParser
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tools [AMDGPU] Set SchedRW on real instructions 2021-03-23 15:38:11 +00:00
.clang-format
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CMakeLists.txt Revert "[IRSim] Adding basic implementation of llvm-sim." 2021-03-20 18:03:09 -05:00
TestRunner.sh
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lit.cfg.py Revert "[IRSim] Adding basic implementation of llvm-sim." 2021-03-20 18:03:09 -05:00
lit.site.cfg.py.in [test] Add ability to get error messages from CMake for errc substitution 2021-03-15 20:56:08 +01:00