forked from OSchip/llvm-project
4773dd5ba9
There is a bunch of similar bitfield extraction code throughout *ISelDAGToDAG. E.g, ARMISelDAGToDAG, AArch64ISelDAGToDAG, and AMDGPUISelDAGToDAG all contain code that matches a bitfield extract from an and + right shift. Rather than duplicating code in the same way, this adds two opcodes: - G_UBFX (unsigned bitfield extract) - G_SBFX (signed bitfield extract) They work like this ``` %x = G_UBFX %y, %lsb, %width ``` Where `lsb` and `width` are - The least-significant bit of the extraction - The width of the extraction This will extract `width` bits from `%y`, starting at `lsb`. G_UBFX zero-extends the result, while G_SBFX sign-extends the result. This should allow us to use the combiner to match the bitfield extraction patterns rather than duplicating pattern-matching code in each target. Differential Revision: https://reviews.llvm.org/D98464 |
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| .. | ||
| GMIR.rst | ||
| GenericOpcode.rst | ||
| IRTranslator.rst | ||
| InstructionSelect.rst | ||
| KnownBits.rst | ||
| Legalizer.rst | ||
| Pipeline.rst | ||
| Porting.rst | ||
| RegBankSelect.rst | ||
| Resources.rst | ||
| block-extract.png | ||
| index.rst | ||
| pipeline-overview-customized.png | ||
| pipeline-overview-with-combiners.png | ||
| pipeline-overview.png | ||
| testing-pass-level.png | ||
| testing-unit-level.png | ||
