forked from OSchip/llvm-project
78 lines
2.3 KiB
LLVM
78 lines
2.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; Check latencies of vmul/vfma accumulate chains.
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define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test1:BB#0
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; CHECK: VMULS
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; > VMULS common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: data
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; > VMULS read-advanced latency to VMLAS = 0
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; CHECK-SAME: Latency=0
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; CHECK: VMLAS
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; > VMLAS common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLAS read-advanced latency to the next VMLAS = 4
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; CHECK-SAME: Latency=4
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; CHECK: VMLAS
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLAS not-optimized latency to VMOVRS = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS
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%mul1 = fmul float %f1, %f2
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%mul2 = fmul float %f3, %f4
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%mul3 = fmul float %f5, %f6
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%add1 = fadd float %mul1, %mul2
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%add2 = fadd float %add1, %mul3
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ret float %add2
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}
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; ASIMD form
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define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test2:BB#0
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; CHECK: VMULfd
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; > VMULfd common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: data
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; VMULfd read-advanced latency to VMLAfd = 0
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; CHECK-SAME: Latency=0
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; CHECK: VMLAfd
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; > VMLAfd common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLAfd read-advanced latency to the next VMLAfd = 4
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; CHECK-SAME: Latency=4
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; CHECK: VMLAfd
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: data
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; > VMLAfd not-optimized latency to VMOVRRD = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS
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%mul1 = fmul <2 x float> %f1, %f2
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%mul2 = fmul <2 x float> %f3, %f4
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%mul3 = fmul <2 x float> %f5, %f6
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%add1 = fadd <2 x float> %mul1, %mul2
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%add2 = fadd <2 x float> %add1, %mul3
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ret <2 x float> %add2
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}
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