forked from OSchip/llvm-project
129 lines
3.8 KiB
YAML
129 lines
3.8 KiB
YAML
# RUN: llc -mtriple=powerpc64le-unknown-unknown -start-before ppc-pre-emit-peephole \
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# RUN: -verify-machineinstrs -ppc-asm-full-reg-names %s -o - | FileCheck %s
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--- |
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; ModuleID = 't.ll'
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source_filename = "t.ll"
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target datalayout = "e-m:e-i64:64-n32:64"
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define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) {
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entry:
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%cmp = icmp slt i32 %a, %b
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp slt i32 %b, %a
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br i1 %cmp1, label %return, label %if.end3
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if.end3: ; preds = %if.end
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%cmp4 = icmp eq i32 %a, %c
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br i1 %cmp4, label %if.then5, label %if.end6
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if.then5: ; preds = %if.end3
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%add = shl nsw i32 %a, 1
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br label %return
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if.end6: ; preds = %if.end3
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%cmp7 = icmp sgt i32 %c, %b
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%add11 = add i32 %c, %b
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%add12 = select i1 %cmp7, i32 %a, i32 0
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%spec.select = add i32 %add11, %add12
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ret i32 %spec.select
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return: ; preds = %if.then5, %if.end, %entry
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%retval.0 = phi i32 [ %add, %if.then5 ], [ %c, %entry ], [ %b, %if.end ]
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ret i32 %retval.0
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}
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...
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---
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name: test
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$x3', virtual-reg: '' }
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- { reg: '$x4', virtual-reg: '' }
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- { reg: '$x5', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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successors: %bb.4(0x40000000), %bb.1(0x40000000)
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liveins: $x3, $x4, $x5
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renamable $cr0 = CMPW renamable $r3, renamable $r4
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BCC 12, renamable $cr0, %bb.4
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bb.1.if.end:
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successors: %bb.6(0x40000000), %bb.2(0x40000000)
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liveins: $cr0, $x3, $x4, $x5
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BCC 36, killed renamable $cr0, %bb.2
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bb.6:
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liveins: $x4
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; CHECK: mr r5, r4
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; CHECK-NOT: mr r5, r5
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; CHECK: extsw r3, r5
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$r5 = OR killed $r4, $r4, implicit $x4, implicit-def $x5
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$r5 = OR $r5, $r5, implicit-def $x5
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renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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bb.2.if.end3:
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successors: %bb.3(0x40000000), %bb.5(0x40000000)
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liveins: $x3, $x4, $x5
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renamable $cr0 = CMPLW renamable $r3, renamable $r5
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BCC 68, killed renamable $cr0, %bb.5
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bb.3.if.then5:
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successors: %bb.4(0x80000000)
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liveins: $x3
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renamable $r5 = RLWINM killed renamable $r3, 1, 0, 30, implicit $x3, implicit-def $x5
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bb.4.return:
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liveins: $x5
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renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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bb.5.if.end6:
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liveins: $x3, $x4, $x5
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renamable $cr0 = CMPW renamable $r5, renamable $r4
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renamable $r6 = LI 0
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renamable $r4 = ADD4 killed renamable $r5, killed renamable $r4, implicit $x4, implicit $x5
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renamable $r3 = ISEL killed renamable $r3, killed renamable $r6, killed renamable $cr0gt, implicit $cr0, implicit $x3
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renamable $r3 = ADD4 killed renamable $r4, killed renamable $r3
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renamable $x3 = EXTSW_32_64 killed renamable $r3
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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...
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