forked from OSchip/llvm-project
275 lines
9.8 KiB
LLVM
275 lines
9.8 KiB
LLVM
; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: < %s | FileCheck %s --check-prefix=P9BE
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; Function Attrs: norecurse nounwind readonly
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define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
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; CHECK-LABEL: test_pre_inc_disable_1:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis r6, r2
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; CHECK: addis r7, r2,
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; CHECK: lfd f0, 0(r5)
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; CHECK: xxlxor v4, v4, v4
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; CHECK: addi r5, r6,
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; CHECK: addi r6, r7,
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; CHECK: lxvx v2, 0, r5
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; CHECK: lxvx v3, 0, r6
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; CHECK: xxpermdi v5, f0, f0, 2
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; CHECK: vperm v0, v4, v5, v2
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; CHECK: vperm v5, v5, v4, v3
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; CHECK: xvnegsp v5, v5
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; CHECK: xvnegsp v0, v0
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; CHECK: .LBB0_1: # %for.cond1.preheader
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; CHECK: lfd f0, 0(r3)
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; CHECK: xxpermdi v1, f0, f0, 2
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; CHECK: vperm v6, v1, v4, v3
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; CHECK: vperm v1, v4, v1, v2
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; CHECK: xvnegsp v6, v6
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; CHECK: xvnegsp v1, v1
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; CHECK: vabsduw v1, v1, v0
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; CHECK: vabsduw v6, v6, v5
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; CHECK: vadduwm v1, v6, v1
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; CHECK: xxswapd v6, v1
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; CHECK: vadduwm v1, v1, v6
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; CHECK: xxspltw v6, v1, 2
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; CHECK: vadduwm v1, v1, v6
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; CHECK: vextuwrx r7, r6, v1
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; CHECK: ldux r8, r3, r4
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; CHECK: add r3, r3, r4
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; CHECK: add r5, r7, r5
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; CHECK: mtvsrd f0, r8
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; CHECK: xxswapd v1, vs0
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; CHECK: vperm v6, v1, v4, v3
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; CHECK: vperm v1, v4, v1, v2
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; CHECK: xvnegsp v6, v6
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; CHECK: xvnegsp v1, v1
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; CHECK: vabsduw v1, v1, v0
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; CHECK: vabsduw v6, v6, v5
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; CHECK: vadduwm v1, v6, v1
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; CHECK: xxswapd v6, v1
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; CHECK: vadduwm v1, v1, v6
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; CHECK: xxspltw v6, v1, 2
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; CHECK: vadduwm v1, v1, v6
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; CHECK: vextuwrx r8, r6, v1
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; CHECK: add r5, r8, r5
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; CHECK: bdnz .LBB0_1
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; CHECK: extsw r3, r5
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; CHECK: blr
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; P9BE-LABEL: test_pre_inc_disable_1:
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; P9BE: addis r6, r2,
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; P9BE: addis r7, r2,
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; P9BE: lfd f0, 0(r5)
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; P9BE: xxlxor v4, v4, v4
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; P9BE: addi r5, r6,
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; P9BE: addi r6, r7,
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; P9BE: lxvx v2, 0, r5
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; P9BE: lxvx v3, 0, r6
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; P9BE: xxlor v5, vs0, vs0
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; P9BE: li r6, 0
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; P9BE: vperm v0, v4, v5, v2
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; P9BE: vperm v5, v4, v5, v3
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; P9BE: xvnegsp v5, v5
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; P9BE: xvnegsp v0, v0
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; P9BE: .LBB0_1: # %for.cond1.preheader
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; P9BE: lfd f0, 0(r3)
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; P9BE: xxlor v1, vs0, vs0
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; P9BE: vperm v6, v4, v1, v3
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; P9BE: vperm v1, v4, v1, v2
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; P9BE: xvnegsp v6, v6
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; P9BE: xvnegsp v1, v1
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; P9BE: vabsduw v1, v1, v0
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; P9BE: vabsduw v6, v6, v5
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; P9BE: vadduwm v1, v6, v1
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; P9BE: xxswapd v6, v1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: xxspltw v6, v1, 1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: vextuwlx r7, r6, v1
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; P9BE: ldux r8, r3, r4
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; P9BE: add r3, r3, r4
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; P9BE: add r5, r7, r5
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; P9BE: mtvsrd v1, r8
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; P9BE: vperm v6, v4, v1, v3
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; P9BE: vperm v1, v4, v1, v2
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; P9BE: xvnegsp v6, v6
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; P9BE: xvnegsp v1, v1
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; P9BE: vabsduw v1, v1, v0
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; P9BE: vabsduw v6, v6, v5
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; P9BE: vadduwm v1, v6, v1
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; P9BE: xxswapd v6, v1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: xxspltw v6, v1, 1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: vextuwlx r8, r6, v1
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; P9BE: add r5, r8, r5
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; P9BE: bdnz .LBB0_1
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; P9BE: extsw r3, r5
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; P9BE: blr
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entry:
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%idx.ext = sext i32 %i_stride_pix1 to i64
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%0 = bitcast i8* %pix2 to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0, align 1
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%2 = zext <8 x i8> %1 to <8 x i32>
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br label %for.cond1.preheader
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for.cond1.preheader: ; preds = %for.cond1.preheader, %entry
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%y.024 = phi i32 [ 0, %entry ], [ %inc9.1, %for.cond1.preheader ]
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%i_sum.023 = phi i32 [ 0, %entry ], [ %op.extra.1, %for.cond1.preheader ]
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%pix1.addr.022 = phi i8* [ %pix1, %entry ], [ %add.ptr.1, %for.cond1.preheader ]
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%3 = bitcast i8* %pix1.addr.022 to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3, align 1
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%5 = zext <8 x i8> %4 to <8 x i32>
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%6 = sub nsw <8 x i32> %5, %2
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%7 = icmp slt <8 x i32> %6, zeroinitializer
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%8 = sub nsw <8 x i32> zeroinitializer, %6
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%9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
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%rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
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%rdx.shuf32 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx33 = add nsw <8 x i32> %bin.rdx, %rdx.shuf32
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%rdx.shuf34 = shufflevector <8 x i32> %bin.rdx33, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx35 = add nsw <8 x i32> %bin.rdx33, %rdx.shuf34
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%10 = extractelement <8 x i32> %bin.rdx35, i32 0
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%op.extra = add nsw i32 %10, %i_sum.023
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%add.ptr = getelementptr inbounds i8, i8* %pix1.addr.022, i64 %idx.ext
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%11 = bitcast i8* %add.ptr to <8 x i8>*
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%12 = load <8 x i8>, <8 x i8>* %11, align 1
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%13 = zext <8 x i8> %12 to <8 x i32>
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%14 = sub nsw <8 x i32> %13, %2
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%15 = icmp slt <8 x i32> %14, zeroinitializer
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%16 = sub nsw <8 x i32> zeroinitializer, %14
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%17 = select <8 x i1> %15, <8 x i32> %16, <8 x i32> %14
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%rdx.shuf.1 = shufflevector <8 x i32> %17, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx.1 = add nsw <8 x i32> %17, %rdx.shuf.1
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%rdx.shuf32.1 = shufflevector <8 x i32> %bin.rdx.1, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx33.1 = add nsw <8 x i32> %bin.rdx.1, %rdx.shuf32.1
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%rdx.shuf34.1 = shufflevector <8 x i32> %bin.rdx33.1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx35.1 = add nsw <8 x i32> %bin.rdx33.1, %rdx.shuf34.1
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%18 = extractelement <8 x i32> %bin.rdx35.1, i32 0
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%op.extra.1 = add nsw i32 %18, %op.extra
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%add.ptr.1 = getelementptr inbounds i8, i8* %add.ptr, i64 %idx.ext
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%inc9.1 = add nuw nsw i32 %y.024, 2
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%exitcond.1 = icmp eq i32 %inc9.1, 8
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br i1 %exitcond.1, label %for.cond.cleanup, label %for.cond1.preheader
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for.cond.cleanup: ; preds = %for.cond1.preheader
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ret i32 %op.extra.1
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}
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; Function Attrs: norecurse nounwind readonly
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define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
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; CHECK-LABEL: test_pre_inc_disable_2:
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; CHECK: addis r5, r2,
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; CHECK: addis r6, r2,
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; CHECK: lfd f0, 0(r3)
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; CHECK: lfd f1, 0(r4)
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; CHECK: xxlxor v0, v0, v0
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; CHECK: addi r3, r5, .LCPI1_0@toc@l
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; CHECK: addi r4, r6, .LCPI1_1@toc@l
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; CHECK: lxvx v2, 0, r3
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; CHECK: lxvx v3, 0, r4
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; CHECK: xxpermdi v4, f0, f0, 2
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; CHECK: xxpermdi v5, f1, f1, 2
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; CHECK: vperm v1, v4, v0, v2
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; CHECK: vperm v4, v0, v4, v3
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; CHECK: vperm v2, v5, v0, v2
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; CHECK: vperm v3, v0, v5, v3
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; CHECK: xvnegsp v5, v1
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; CHECK: xvnegsp v4, v4
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; CHECK: xvnegsp v2, v2
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; CHECK: xvnegsp v3, v3
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; CHECK: vabsduw v3, v4, v3
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; CHECK: vabsduw v2, v5, v2
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; CHECK: vadduwm v2, v2, v3
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; CHECK: xxswapd v3, v2
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; CHECK: vadduwm v2, v2, v3
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; CHECK: xxspltw v3, v2, 2
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; CHECK: vadduwm v2, v2, v3
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; CHECK: vextuwrx r3, r3, v2
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; CHECK: extsw r3, r3
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; CHECK: blr
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; P9BE-LABEL: test_pre_inc_disable_2:
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; P9BE: addis r5, r2,
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; P9BE: addis r6, r2,
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; P9BE: lfd f0, 0(r3)
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; P9BE: lfd f1, 0(r4)
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; P9BE: xxlxor v5, v5, v5
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; P9BE: addi r3, r5,
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; P9BE: addi r4, r6,
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; P9BE: lxvx v2, 0, r3
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; P9BE: lxvx v3, 0, r4
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; P9BE: xxlor v4, vs0, vs0
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; P9BE: xxlor v0, vs1, vs1
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; P9BE: vperm v1, v5, v4, v2
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; P9BE: vperm v4, v5, v4, v3
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; P9BE: vperm v2, v5, v0, v2
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; P9BE: vperm v3, v5, v0, v3
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; P9BE: xvnegsp v5, v1
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; P9BE: xvnegsp v4, v4
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; P9BE: xvnegsp v2, v2
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; P9BE: xvnegsp v3, v3
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; P9BE: vabsduw v3, v4, v3
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; P9BE: vabsduw v2, v5, v2
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; P9BE: vadduwm v2, v2, v3
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; P9BE: xxswapd v3, v2
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; P9BE: vadduwm v2, v2, v3
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; P9BE: xxspltw v3, v2, 1
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; P9BE: vadduwm v2, v2, v3
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; P9BE: vextuwlx r3, r3, v2
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; P9BE: extsw r3, r3
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; P9BE: blr
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entry:
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%0 = bitcast i8* %pix1 to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0, align 1
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%2 = zext <8 x i8> %1 to <8 x i32>
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%3 = bitcast i8* %pix2 to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3, align 1
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%5 = zext <8 x i8> %4 to <8 x i32>
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%6 = sub nsw <8 x i32> %2, %5
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%7 = icmp slt <8 x i32> %6, zeroinitializer
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%8 = sub nsw <8 x i32> zeroinitializer, %6
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%9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
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%rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
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%rdx.shuf12 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx13 = add nsw <8 x i32> %bin.rdx, %rdx.shuf12
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%rdx.shuf14 = shufflevector <8 x i32> %bin.rdx13, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx15 = add nsw <8 x i32> %bin.rdx13, %rdx.shuf14
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%10 = extractelement <8 x i32> %bin.rdx15, i32 0
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ret i32 %10
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}
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; Generated from C source:
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;
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;#include <stdint.h>
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;#include <stdlib.h>
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;int test_pre_inc_disable_1( uint8_t *pix1, int i_stride_pix1, uint8_t *pix2 ) {
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; int i_sum = 0;
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; for( int y = 0; y < 8; y++ ) {
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; for( int x = 0; x < 8; x++) {
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; i_sum += abs( pix1[x] - pix2[x] )
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; }
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; pix1 += i_stride_pix1;
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; }
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; return i_sum;
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;}
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;int test_pre_inc_disable_2( uint8_t *pix1, uint8_t *pix2 ) {
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; int i_sum = 0;
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; for( int x = 0; x < 8; x++ ) {
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; i_sum += abs( pix1[x] - pix2[x] );
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; }
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;
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; return i_sum;
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;}
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