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AsmParser
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[AArch64] Add IR intrinsics for sq(r)dmulh_lane(q)
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2020-01-29 13:25:23 +00:00 |
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Disassembler
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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MCTargetDesc
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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Utils
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[AArch64][SVE] Add patterns for unpredicated load/store to frame-indices.
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2020-01-22 14:32:27 +00:00 |
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AArch64.h
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GlobalISel: add combiner to form indexed loads.
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2019-09-09 10:04:23 +00:00 |
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AArch64.td
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AArch64: add missing Apple CPU names and use them by default.
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2020-01-08 09:24:06 +00:00 |
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AArch64A53Fix835769.cpp
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…
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AArch64A57FPLoadBalancing.cpp
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[llvm] Migrate llvm::make_unique to std::make_unique
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2019-08-15 15:54:37 +00:00 |
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AArch64AdvSIMDScalarPass.cpp
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[aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-12 22:40:53 +00:00 |
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AArch64AsmPrinter.cpp
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[AArch64] -fpatchable-function-entry=N,0: place patch label after BTI
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2020-01-30 11:11:52 -08:00 |
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AArch64BranchTargets.cpp
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…
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AArch64CallLowering.cpp
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[GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister
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2020-01-31 17:07:16 +00:00 |
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AArch64CallLowering.h
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[AArch64][GlobalISel][NFC] Refactor tail call lowering code
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2019-09-17 19:08:44 +00:00 |
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AArch64CallingConvention.cpp
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[Alignment][NFC] Remove unneeded llvm:: scoping on Align types
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2019-09-27 12:54:21 +00:00 |
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AArch64CallingConvention.h
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Add Windows Control Flow Guard checks (/guard:cf).
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2019-10-28 15:19:39 +00:00 |
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AArch64CallingConvention.td
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[AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal types
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2019-12-12 09:49:22 +00:00 |
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AArch64CleanupLocalDynamicTLSPass.cpp
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…
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AArch64CollectLOH.cpp
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AArch64: support arm64_32, an ILP32 slice for watchOS.
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2019-09-12 10:22:23 +00:00 |
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AArch64Combine.td
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[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS
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2020-01-16 15:18:44 -08:00 |
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AArch64CompressJumpTables.cpp
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[Alignment][NFC] Deprecate Align::None()
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2020-01-24 12:53:58 +01:00 |
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AArch64CondBrTuning.cpp
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[aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-12 22:40:53 +00:00 |
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AArch64ConditionOptimizer.cpp
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Update spelling of {analyze,insert,remove}Branch in strings and comments
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2020-01-21 10:15:38 -06:00 |
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AArch64ConditionalCompares.cpp
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Update spelling of {analyze,insert,remove}Branch in strings and comments
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2020-01-21 10:15:38 -06:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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[aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-12 22:40:53 +00:00 |
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AArch64ExpandImm.cpp
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…
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AArch64ExpandImm.h
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…
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AArch64ExpandPseudoInsts.cpp
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[Fuchsia] Remove aarch64-fuchsia target-specific -mcmodel=kernel
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2020-01-28 11:32:08 -08:00 |
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AArch64FalkorHWPFFix.cpp
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[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
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2020-01-19 14:20:37 -08:00 |
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AArch64FastISel.cpp
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[AArch64] [Windows] Use COFF stubs for calls to extern_weak functions
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2019-12-23 12:13:49 +02:00 |
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AArch64FrameLowering.cpp
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Merge memtag instructions with adjacent stack slots.
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2020-01-17 15:19:29 -08:00 |
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AArch64FrameLowering.h
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Merge memtag instructions with adjacent stack slots.
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2020-01-17 15:19:29 -08:00 |
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AArch64GenRegisterBankInfo.def
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[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms.
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2019-07-03 01:49:06 +00:00 |
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AArch64ISelDAGToDAG.cpp
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[AArch64][SVE] Add patterns for unpredicated load/store to frame-indices.
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2020-01-22 14:32:27 +00:00 |
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AArch64ISelLowering.cpp
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[NFC] Encapsulate MemOp logic
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2020-02-04 10:36:26 +01:00 |
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AArch64ISelLowering.h
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[NFC] Introduce a type to model memory operation
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2020-01-31 17:29:01 +01:00 |
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AArch64InstrAtomics.td
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DAG: Use TargetConstant for FENCE operands
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2020-01-02 17:16:10 -05:00 |
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AArch64InstrFormats.td
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[AArch64][SVE] Add remaining SVE2 intrinsics for uniform DSP operations
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2020-01-31 10:51:57 +00:00 |
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AArch64InstrInfo.cpp
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[NFC] unsigned->Register in storeRegTo/loadRegFromStack
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2020-02-03 14:22:16 +01:00 |
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AArch64InstrInfo.h
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[NFC] unsigned->Register in storeRegTo/loadRegFromStack
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2020-02-03 14:22:16 +01:00 |
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AArch64InstrInfo.td
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[FPEnv][AArch64] Add lowering and instruction selection for strict conversions
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2020-01-30 13:50:06 +00:00 |
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AArch64InstructionSelector.cpp
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[AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation
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2020-02-03 15:22:24 -08:00 |
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AArch64LegalizerInfo.cpp
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[GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister
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2020-01-31 17:07:16 +00:00 |
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AArch64LegalizerInfo.h
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GlobalISel: Add observer argument to legalizeIntrinsic
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2020-01-29 18:33:45 -05:00 |
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AArch64LoadStoreOptimizer.cpp
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[AArch64] Add option to enable/disable load-store renaming.
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2020-01-27 15:15:50 -08:00 |
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AArch64MCInstLower.cpp
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AArch64: Add a tagged-globals backend feature.
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2019-07-31 20:14:19 +00:00 |
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AArch64MCInstLower.h
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…
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AArch64MachineFunctionInfo.h
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Revert "AArch64: Fix frame record chain"
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2019-12-14 13:58:40 -08:00 |
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AArch64MacroFusion.cpp
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…
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AArch64MacroFusion.h
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…
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AArch64PBQPRegAlloc.cpp
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[aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-12 22:40:53 +00:00 |
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AArch64PBQPRegAlloc.h
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…
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AArch64PerfectShuffle.h
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…
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AArch64PfmCounters.td
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…
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AArch64PreLegalizerCombiner.cpp
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[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS
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2020-01-16 15:18:44 -08:00 |
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AArch64PromoteConstant.cpp
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Sink all InitializePasses.h includes
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2019-11-13 16:34:37 -08:00 |
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AArch64RedundantCopyElimination.cpp
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…
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AArch64RegisterBankInfo.cpp
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Revert "Reland "[AArch64] Fix data race on RegisterBank initialization.""
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2020-02-03 16:58:58 -08:00 |
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AArch64RegisterBankInfo.h
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GlobalISel: Add type argument to getRegBankFromRegClass
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2020-01-03 16:25:10 -05:00 |
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AArch64RegisterBanks.td
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…
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AArch64RegisterInfo.cpp
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[AArch64] Add IR intrinsics for sq(r)dmulh_lane(q)
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2020-01-29 13:25:23 +00:00 |
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AArch64RegisterInfo.h
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[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
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2020-01-19 14:20:37 -08:00 |
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AArch64RegisterInfo.td
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[AArch64] Add IR intrinsics for sq(r)dmulh_lane(q)
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2020-01-29 13:25:23 +00:00 |
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AArch64SIMDInstrOpt.cpp
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Make llvm::StringRef to std::string conversions explicit.
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2020-01-28 23:25:25 +01:00 |
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Add SVE2 mla unpredicated intrinsics.
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2020-01-31 11:39:12 -05:00 |
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AArch64SchedA53.td
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…
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AArch64SchedA57.td
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…
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AArch64SchedA57WriteRes.td
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…
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AArch64SchedCyclone.td
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…
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AArch64SchedExynosM3.td
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[AArch64] Update for Exynos
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2019-11-12 14:37:41 -06:00 |
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AArch64SchedExynosM4.td
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[AArch64] Update for Exynos
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2019-11-12 14:37:41 -06:00 |
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AArch64SchedExynosM5.td
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[AArch64] Add the pipeline model for Exynos M5
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2019-11-22 15:09:17 -06:00 |
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AArch64SchedFalkor.td
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…
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AArch64SchedFalkorDetails.td
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…
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AArch64SchedKryo.td
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…
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AArch64SchedKryoDetails.td
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…
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AArch64SchedPredExynos.td
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[AArch64] Add new scheduling predicates
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2019-11-11 15:02:51 -06:00 |
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AArch64SchedPredicates.td
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[NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp
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2019-11-23 19:11:31 +01:00 |
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AArch64SchedThunderX.td
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AArch64SchedThunderX2T99.td
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[AArch64] Remove overlapping scheduling definitions (NFC)
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2019-10-30 13:57:27 -05:00 |
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AArch64Schedule.td
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…
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AArch64SelectionDAGInfo.cpp
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Merge memtag instructions with adjacent stack slots.
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2020-01-17 15:19:29 -08:00 |
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AArch64SelectionDAGInfo.h
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Basic codegen for MTE stack tagging.
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2019-07-17 19:24:02 +00:00 |
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AArch64SpeculationHardening.cpp
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Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
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2019-10-19 01:31:09 +00:00 |
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AArch64StackOffset.h
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[SVE][CodeGen] Scalable vector MVT size queries
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2019-11-18 12:30:59 +00:00 |
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AArch64StackTagging.cpp
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[IR] Split out target specific intrinsic enums into separate headers
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2019-12-11 18:02:14 -08:00 |
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AArch64StackTaggingPreRA.cpp
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MTE: add more unchecked instructions.
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2019-11-19 11:19:53 -08:00 |
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AArch64StorePairSuppress.cpp
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[aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-12 22:40:53 +00:00 |
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AArch64Subtarget.cpp
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AArch64: add missing Apple CPU names and use them by default.
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2020-01-08 09:24:06 +00:00 |
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AArch64Subtarget.h
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AArch64: add missing Apple CPU names and use them by default.
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2020-01-08 09:24:06 +00:00 |
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AArch64SystemOperands.td
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AArch64: add missing Apple CPU names and use them by default.
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2020-01-08 09:24:06 +00:00 |
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AArch64TargetMachine.cpp
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[Fuchsia] Remove aarch64-fuchsia target-specific -mcmodel=kernel
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2020-01-28 11:32:08 -08:00 |
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AArch64TargetMachine.h
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…
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AArch64TargetObjectFile.cpp
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Revert "Honor -fuse-init-array when os is not specified on x86"
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2019-12-17 07:36:59 -08:00 |
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AArch64TargetObjectFile.h
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[MachO][TLOF] Use hasLocalLinkage to determine if indirect symbol is local
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2019-08-22 16:59:00 +00:00 |
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AArch64TargetTransformInfo.cpp
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[IR] Split out target specific intrinsic enums into separate headers
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2019-12-11 18:02:14 -08:00 |
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AArch64TargetTransformInfo.h
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[AArch64][ARM] Always expand ordered vector reductions (PR44600)
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2020-01-30 18:40:24 +01:00 |
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CMakeLists.txt
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[gicombiner] Fix windows issue where single quotes in the command are passed through to tablegen
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2019-10-02 23:38:06 +00:00 |
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LLVMBuild.txt
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Add Windows Control Flow Guard checks (/guard:cf).
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2019-10-28 15:19:39 +00:00 |
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SVEInstrFormats.td
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[AArch64][SVE] Add SVE2 mla unpredicated intrinsics.
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2020-01-31 11:39:12 -05:00 |
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