forked from OSchip/llvm-project
51 lines
1.6 KiB
LLVM
51 lines
1.6 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; This testcase used to fail with "cannot select 'i1 = add x, y'".
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; Check for some sane output:
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; CHECK: xor(p{{[0-3]}},p{{[0-3]}})
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define void @foo(i32* nocapture %a0) local_unnamed_addr #0 {
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b1:
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%v2 = getelementptr inbounds i32, i32* %a0, i32 26
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%v3 = load i32, i32* %v2, align 4
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%v4 = add nsw i32 %v3, 1
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%v5 = load i32, i32* %a0, align 4
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br label %b6
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b6: ; preds = %b28, %b1
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%v7 = phi i32 [ %v29, %b28 ], [ %v5, %b1 ]
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%v8 = mul nsw i32 %v4, %v7
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%v9 = add nsw i32 %v8, %v7
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%v10 = mul i32 %v7, %v7
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%v11 = mul i32 %v10, %v9
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%v12 = add nsw i32 %v11, 1
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%v13 = mul nsw i32 %v12, %v7
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%v14 = add nsw i32 %v13, %v7
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%v15 = mul i32 %v10, %v14
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%v16 = and i32 %v15, 1
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%v17 = add nsw i32 %v16, -1
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%v18 = mul i32 %v10, %v7
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%v19 = mul i32 %v18, %v11
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%v20 = mul i32 %v19, %v17
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%v21 = and i32 %v20, 1
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%v22 = add nsw i32 %v21, -1
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%v23 = mul nsw i32 %v22, %v3
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%v24 = sub nsw i32 %v7, %v23
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%v25 = mul i32 %v10, %v24
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%v26 = sub i32 0, %v7
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%v27 = icmp eq i32 %v25, %v26
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br i1 %v27, label %b30, label %b28
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b28: ; preds = %b6
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%v29 = add nsw i32 %v3, %v7
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store i32 %v29, i32* %a0, align 4
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br label %b6
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b30: ; preds = %b6
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ret void
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" }
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