forked from OSchip/llvm-project
92 lines
3.3 KiB
ArmAsm
92 lines
3.3 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid result type.
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ldnt1b { z0.b }, p0/z, [z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b { z0.h }, p0/z, [z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b { z0.h }, p0/z, [z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid base vector.
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ldnt1b { z0.s }, p0/z, [z0.b]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.b]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b { z0.d }, p0/z, [z0.h]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.h]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid offset type.
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ldnt1b { z0.d }, p0/z, [z0.d, z1.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, z1.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate operation
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ldnt1b { z0.d }, p0/m, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b { z0.d }, p0/m, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ldnt1b { z27.d }, p8/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ldnt1b { z27.d }, p8/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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ldnt1b { }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ldnt1b { }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b { z0.d, z1.d }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b { z0.d, z1.d }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b { v0.2d }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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ldnt1b { z0.d }, p0/z, [z0.d, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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ldnt1b { z0.s }, p0/z, [z0.s, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.s, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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