..
AArch64
Revert "[AArch64] Homogeneous Prolog and Epilog Size Optimization"
2021-02-02 02:33:44 -05:00
AMDGPU
[AMDGPU] Save fp/bp after csr saves
2021-02-02 17:17:54 +01:00
ARC
…
ARM
[ARM] Simplify VMOVRRD from extracts of buildvectors
2021-02-01 16:09:25 +00:00
AVR
[AVR] Optimize 16-bit int shift
2021-01-28 15:10:11 +08:00
BPF
…
Generic
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
Hexagon
[NewPM][opt] Run the "default" AA pipeline by default
2021-01-21 21:08:54 -08:00
Inputs
…
Lanai
…
MIR
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
MSP430
…
Mips
[CodeGen] Try to make the print of memory operand alignment a little more user friendly.
2021-01-11 19:58:47 -08:00
NVPTX
[NFC] Disallow unused prefixes under llvm/test/CodeGen
2021-01-11 12:32:18 -08:00
PowerPC
[PowerPC] Materialize 34 bit constants with pli on Power 10.
2021-02-02 09:49:22 -06:00
RISCV
[RISCV] Add scalable vector support for floating point FMA instructions
2021-02-01 09:52:43 -08:00
SPARC
[SPARC] Fix fp128 load/stores
2021-01-13 14:59:50 -08:00
SystemZ
[SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds
2021-01-14 15:46:27 +00:00
Thumb
[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
2021-01-23 09:10:03 +00:00
Thumb2
[ARM] Add MVE insert-of-extract pattern
2021-02-02 15:15:04 +00:00
VE
[VE] Update VELIntrinsic tests
2021-01-13 00:12:50 +09:00
WebAssembly
[WebAssembly] Prototype i8x16 to i32x4 widening instructions
2021-01-28 10:59:32 -08:00
WinCFGuard
…
WinEH
…
X86
[X86][AVX512] Support variable-index vector insertion on AVX512 targets (PR47924)
2021-02-02 11:41:18 +00:00
XCore
[test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:47:16 -08:00