forked from OSchip/llvm-project
50 lines
1.2 KiB
YAML
50 lines
1.2 KiB
YAML
# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -o - 2>&1 | FileCheck %s
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# REQUIRES: global-isel
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--- |
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; ModuleID = 'generic-virtual-registers-type-error.mir'
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-apple-ios"
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define void @defaultMapping() {
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entry:
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ret void
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}
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define void @defaultMappingVector() {
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entry:
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ret void
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}
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...
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---
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# Check that we assign a relevant register bank for %0.
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# Based on the type i32, this should be gpr.
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name: defaultMapping
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0
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; CHECK: %0(32) = G_ADD i32 %x0
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%0(32) = G_ADD i32 %x0, %x0
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...
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---
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# Check that we assign a relevant register bank for %0.
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# Based on the type <2 x i32>, this should be fpr.
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# FPR is used for both floating point and vector registers.
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name: defaultMappingVector
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0.entry:
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liveins: %d0
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; CHECK: %0(32) = G_ADD <2 x i32> %d0
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%0(32) = G_ADD <2 x i32> %d0, %d0
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...
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