forked from OSchip/llvm-project
36 lines
1.3 KiB
ArmAsm
36 lines
1.3 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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fmaxnmv b0, p7, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fmaxnmv b0, p7, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmaxnmv h0, p8, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: fmaxnmv h0, p8, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Result must be a valid FP register.
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fmaxnmv v0, p7, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fmaxnmv v0, p7, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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fmaxnmv d0, p7, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fmaxnmv d0, p7, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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fmaxnmv d0, p7, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fmaxnmv d0, p7, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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