forked from OSchip/llvm-project
37 lines
1.4 KiB
ArmAsm
37 lines
1.4 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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fadda b0, p7, b0, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fadda b0, p7, b0, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fadda h0, p7, h1, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: fadda h0, p7, h1, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fadda h0, p8, h0, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: fadda h0, p8, h0, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fadda v0.8h, p7, v0.8h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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fadda d0, p7, d0, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fadda d0, p7, d0, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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fadda d0, p7, d0, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fadda d0, p7, d0, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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