forked from OSchip/llvm-project
577a97e2b9
This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c. This is a very first step towards adding PIC support for Linux in the RISC-V backend. The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses For now, this patch only introduces support of that pseudo instruction at the assembler parser. Differential Revision: https://reviews.llvm.org/D49661 llvm-svn: 339314 |
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| .. | ||
| AArch64 | ||
| AMDGPU | ||
| ARM | ||
| AVR | ||
| AsmParser | ||
| BPF | ||
| COFF | ||
| Disassembler | ||
| ELF | ||
| Hexagon | ||
| Lanai | ||
| MachO | ||
| Mips | ||
| PowerPC | ||
| RISCV | ||
| Sparc | ||
| SystemZ | ||
| WebAssembly | ||
| X86 | ||