forked from OSchip/llvm-project
41 lines
1.9 KiB
Plaintext
41 lines
1.9 KiB
Plaintext
// RUN: %clang_cc1 -fcuda-is-device \
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// RUN: -triple nvptx-nvidia-cuda -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix NOFTZ
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// RUN: %clang_cc1 -fcuda-is-device -fcuda-flush-denormals-to-zero \
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// RUN: -triple nvptx-nvidia-cuda -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix FTZ
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// RUN: %clang_cc1 -fcuda-is-device -x hip \
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// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix AMDNOFTZ
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// RUN: %clang_cc1 -fcuda-is-device -x hip -fcuda-flush-denormals-to-zero \
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// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix AMDFTZ
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#include "Inputs/cuda.h"
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// Checks that device function calls get emitted with the "ntpvx-f32ftz"
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// attribute set to "true" when we compile CUDA device code with
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// -fcuda-flush-denormals-to-zero. Further, check that we reflect the presence
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// or absence of -fcuda-flush-denormals-to-zero in a module flag.
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// AMDGCN targets always have +fp64-fp16-denormals.
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// AMDGCN targets without fast FMAF (e.g. gfx803) always have +fp32-denormals.
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// For AMDGCN target with fast FMAF (e.g. gfx900), it has +fp32-denormals
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// by default and -fp32-denormals when there is option
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// -fcuda-flush-denormals-to-zero.
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// CHECK-LABEL: define void @foo() #0
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extern "C" __device__ void foo() {}
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// FTZ: attributes #0 = {{.*}} "nvptx-f32ftz"="true"
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// NOFTZ-NOT: attributes #0 = {{.*}} "nvptx-f32ftz"
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// AMDNOFTZ: attributes #0 = {{.*}}+fp32-denormals{{.*}}+fp64-fp16-denormals
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// AMDFTZ: attributes #0 = {{.*}}+fp64-fp16-denormals{{.*}}-fp32-denormals
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// FTZ:!llvm.module.flags = !{{{.*}}[[MODFLAG:![0-9]+]]}
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// FTZ:[[MODFLAG]] = !{i32 4, !"nvvm-reflect-ftz", i32 1}
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// NOFTZ:!llvm.module.flags = !{{{.*}}[[MODFLAG:![0-9]+]]}
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// NOFTZ:[[MODFLAG]] = !{i32 4, !"nvvm-reflect-ftz", i32 0}
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