forked from OSchip/llvm-project
57 lines
2.5 KiB
LLVM
57 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s
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define arm_aapcs_vfpcc void @fabs(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %blockSize) {
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; CHECK-LABEL: fabs:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: .LBB0_1: @ %vector.ph
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB0_2: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vabs.f32 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r1], #16
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; CHECK-NEXT: letp lr, .LBB0_2
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; CHECK-NEXT: @ %bb.3: @ %while.end
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp3 = icmp eq i32 %blockSize, 0
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br i1 %cmp3, label %while.end, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %blockSize, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %blockSize, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pDst, i32 %index
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%next.gep13 = getelementptr float, float* %pSrcA, i32 %index
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %blockSize)
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%0 = bitcast float* %next.gep13 to <4 x float>*
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
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%1 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.masked.load)
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%2 = bitcast float* %next.gep to <4 x float>*
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call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %while.end, label %vector.body
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while.end: ; preds = %vector.body, %entry
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ret void
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}
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
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declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
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