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llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops
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David Green cb27006a94 [ARM] Attempt to make Tail predication / RDA more resilient to empty blocks 
There are a number of places in RDA where we assume the block will not
be empty. This isn't necessarily true for tail predicated loops where we
have removed instructions. This attempt to make the pass more resilient
to empty blocks, not casting pointers to machine instructions where they
would be invalid.

The test contains a case that was previously failing, but recently been
hidden on trunk. It contains an empty block to begin with to show a
similar error.

Differential Revision: https://reviews.llvm.org/D88926
 		2020-10-10 14:50:25 +01:00
..
add_reduce.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
begin-vpt-without-inst.mir [ARM] Change VPT state assertion 2020-09-30 08:01:10 +01:00
biquad-cascade-default.mir [NFC][ARM] Add more LowOverheadLoop tests. 2020-09-30 12:20:07 +01:00
biquad-cascade-optsize-strd-lr.mir [RDA] isSafeToDefRegAt: Look at global uses 2020-09-30 14:06:45 +01:00
biquad-cascade-optsize.mir [NFC][ARM] Add more LowOverheadLoop tests. 2020-09-30 12:20:07 +01:00
branch-targets.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
clear-maskedinsts.ll [ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks 2020-08-25 14:38:03 +01:00
cmplx_cong.mir [RDA] Track implicit-defs 2020-02-28 11:14:42 +00:00
cond-mov.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
cond-vector-reduce-mve-codegen.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
ctlz-non-zeros.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
disjoint-vcmp.mir [ARM] Fix tail predication predicate tracking 2020-09-16 11:59:29 +01:00
dont-ignore-vctp.mir [RDA] Track implicit-defs 2020-02-28 11:14:42 +00:00
dont-remove-loop-update.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
emptyblock.mir [ARM] Attempt to make Tail predication / RDA more resilient to empty blocks 2020-10-10 14:50:25 +01:00
end-positive-offset.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
exitcount.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
extending-loads.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
extract-element.mir [ARM][LowOverheadLoops] Liveouts and reductions 2020-08-28 13:56:16 +01:00
fast-fp-loops.ll [ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks 2020-08-25 14:38:03 +01:00
incorrect-sub-8.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
incorrect-sub-16.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
incorrect-sub-32.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
inloop-vpnot-1.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
inloop-vpnot-2.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
inloop-vpnot-3.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
inloop-vpsel-1.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
inloop-vpsel-2.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
invariant-qreg.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
it-block-chain-store.mir [ARM][LowOverheadLoops] Iteration count liveness 2020-10-01 10:11:10 +01:00
it-block-chain.mir [ARM] Fix MIR tests with invalid live-ins. 2020-04-21 12:13:35 -07:00
it-block-itercount.mir [RDA][ARM] collectKilledOperands across multiple blocks 2020-03-03 15:23:05 +00:00
it-block-mov.mir [ARM][LowOverheadLoops] Start insertion point 2020-10-01 10:05:25 +01:00
it-block-random.mir Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
iv-two-vcmp-reordered.mir [NFC][ARM] Add more tail predication tests 2020-05-19 14:01:10 +01:00
iv-two-vcmp.mir [ARM] Check for LSTP side-effects. 2020-09-24 13:28:35 +01:00
iv-vcmp.mir [ARM][LowOverheadLoops] Fix tests after ef0b9f3 2020-09-16 11:01:21 +01:00
livereg-no-loop-def.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
loop-dec-copy-chain.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
loop-dec-copy-prev-iteration.mir [ARM][LowOverheadLoops] Start insertion point 2020-10-01 10:05:25 +01:00
loop-dec-liveout.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
loop-guards.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
lsr-profitable-chain.ll [ARM][MVE] Refactor option -disable-mve-tail-predication 2020-07-13 13:40:33 +01:00
lstp-insertion-position.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
massive.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
matrix-debug.mir [ARM][LowOverheadLoops] Use iterator for InsertPt. 2020-10-01 08:32:35 +01:00
matrix.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mov-after-dls.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
mov-after-dlstp.mir [ARM][LowOverheadLoops] Adjust Start insertion. 2020-10-01 10:49:19 +01:00
mov-lr-terminator.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
mov-operand.ll [ARM][LowOverheadLoops] Adjust Start insertion. 2020-10-01 10:49:19 +01:00
move-def-before-start.mir [ARM][LowOverheadLoops] Adjust Start insertion. 2020-10-01 10:49:19 +01:00
move-start-after-def.mir [ARM][LowOverheadLoops] Adjust Start insertion. 2020-10-01 10:49:19 +01:00
multi-block-cond-iter-count.mir [NFC][ARM] Add tests 2020-02-28 11:24:02 +00:00
multi-cond-iter-count.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
multiblock-massive.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
multiple-do-loops.mir [RDA][ARM] collectKilledOperands across multiple blocks 2020-03-03 15:23:05 +00:00
mve-float-loops.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
mve-tail-data-types.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
nested.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
no-dec-cbnz.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
no-dec-le-simple.ll
…
no-dec-reorder.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
no-dec.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
no-vpsel-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
non-masked-load.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
non-masked-store.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
out-of-range-cbz.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
predicated-invariant.mir [ARM][MVE] Validate tail predication values 2020-03-10 09:59:01 +00:00
predicated-liveout-unknown-lanes.ll [ARM][LowOverheadLoops] Allow tail predication on predicated instructions with unknown lane 2020-09-10 10:34:32 +01:00
predicated-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
reductions-vpt-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
reductions.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
remat-vctp.ll [ARM] Find VPT implicitly predicated by VCTP 2020-09-25 08:50:53 +01:00
remove-elem-moves.mir Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
revert-after-call.mir
…
revert-after-read.mir
…
revert-after-write.mir
…
revert-non-header.mir Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
revert-non-loop.mir
…
revert-while.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
safe-def-no-mov.mir [ARM] Fix MIR tests with invalid live-ins. 2020-04-21 12:13:35 -07:00
safe-retaining.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
sibling-loops.ll [ARM][HWLoops] Create hardware loops for sibling loops 2020-07-03 17:20:02 +01:00
size-limit.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
skip-debug.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
switch.mir Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
tail-pred-basic.ll [ARM][MVE] tail-predication: overflow checks for elementcount, cont'd 2020-09-28 09:20:51 +01:00
tail-pred-const.ll [ARM][MVE] tail-predication: overflow checks for elementcount, cont'd 2020-09-28 09:20:51 +01:00
tail-pred-disabled-in-loloops.ll [ARM] LowoverheadLoops: add an option to disable tail-predication 2020-09-24 13:30:48 +01:00
tail-pred-intrinsic-add-sat.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
tail-pred-intrinsic-fabs.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
tail-pred-intrinsic-round.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
tail-pred-intrinsic-sub-sat.ll [ARM] Fixup of a few test cases. NFC. 2020-09-09 11:14:44 +01:00
tail-pred-narrow.ll [ARM][MVE] Refactor option -disable-mve-tail-predication 2020-07-13 13:40:33 +01:00
tail-pred-pattern-fail.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
tail-pred-reduce.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
tail-pred-widen.ll [ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks 2020-08-25 14:38:03 +01:00
tp-multiple-vpst.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
unpredicated-max.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
unpredload.ll [ARM] Allow tail predication of VLDn 2020-08-18 17:15:45 +01:00
unrolled-and-vector.mir Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
unsafe-cpsr-loop-def.mir Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
unsafe-cpsr-loop-use.mir [ARM] Fix MIR tests with invalid live-ins. 2020-04-21 12:13:35 -07:00
unsafe-liveout.mir [ARM] Fix MIR tests with invalid live-ins. 2020-04-21 12:13:35 -07:00
unsafe-retaining.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
unsafe-use-after.mir [ARM] Fix MIR tests with invalid live-ins. 2020-04-21 12:13:35 -07:00
vaddv.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
varying-outer-2d-reduction.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
vcmp-vpst-combination.ll [ARM][LowOverheadLoops] Combine a VCMP and VPST into a VPT 2020-09-16 09:27:10 +01:00
vctp-add-operand-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
vctp-in-vpt-2.mir [ARM] Improve VPT predicate tracking 2020-09-22 10:40:27 +01:00
vctp-in-vpt.mir [ARM] Remove MVEDomain from VLDR/STR of P0 2020-09-22 09:05:50 +01:00
vctp-subi3.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
vctp-subri.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
vctp-subri12.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
vctp16-reduce.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
vector-arith-codegen.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
vector-reduce-mve-tail.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
vector-unroll.ll [ARM][MVE] Refactor option -disable-mve-tail-predication 2020-07-13 13:40:33 +01:00
vmaxmin_vpred_r.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
vmldava_in_vpt.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
vpt-blocks.mir [ARM] Find VPT implicitly predicated by VCTP 2020-09-25 08:50:53 +01:00
while-negative-offset.mir
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while.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
wlstp.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
wrong-liveout-lsr-shift.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
wrong-vctp-opcode-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
wrong-vctp-operand-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00