llvm-project/llvm/test/CodeGen
jasonliu f85bcc21dd [AIX] Turn -fdata-sections on by default in Clang
Summary:

This patch does the following:
1. Make InitTargetOptionsFromCodeGenFlags() accepts Triple as a
 parameter, because some options' default value is triple dependant.
2. DataSections is turned on by default on AIX for llc.
3. Test cases change accordingly because of the default behaviour change.
4. Clang Driver passes in -fdata-sections by default on AIX.

Reviewed By: MaskRay, DiggerLin

Differential Revision: https://reviews.llvm.org/D88737
2020-10-14 15:58:31 +00:00
..
AArch64 [SVE] Lower fixed length VECREDUCE_FADD operation 2020-10-14 09:41:11 -05:00
AMDGPU [AMDGPU][GlobalISel] Compute known bits for zero-extending loads 2020-10-13 16:22:00 +01:00
ARC [ARC] Update brcc test. 2020-08-28 17:07:25 -07:00
ARM Revert "Reland "[SCEV] Model ptrtoint(SCEVUnknown) cast not as unknown, but as zext/trunc/self of SCEVUnknown"" and it's follow-ups 2020-10-14 16:09:18 +03:00
AVR [AVR] fix interrupt stack pointer restoration 2020-10-01 18:52:13 +13:00
BPF [BPF] Make BPFAbstractMemberAccessPass required 2020-10-09 11:26:37 -07:00
Generic [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
Hexagon [Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR 2020-10-10 19:49:47 -05:00
Inputs
Lanai
MIR Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access" 2020-09-29 15:33:34 +02:00
MSP430
Mips [DAG][ARM][MIPS][RISCV] Improve funnel shift promotion to use 'double shift' patterns 2020-10-12 14:11:02 +01:00
NVPTX
PowerPC [AIX] Turn -fdata-sections on by default in Clang 2020-10-14 15:58:31 +00:00
RISCV [DAG][ARM][MIPS][RISCV] Improve funnel shift promotion to use 'double shift' patterns 2020-10-12 14:11:02 +01:00
SPARC [Sparc] Remove cast that truncates immediate operands to 32 bits. 2020-10-02 20:14:55 -04:00
SystemZ [SystemZ] Bugfix in SystemZVectorConstantInfo 2020-10-14 15:34:40 +02:00
Thumb
Thumb2 [ARM] Attempt to make Tail predication / RDA more resilient to empty blocks 2020-10-10 14:50:25 +01:00
VE [VE] Support copysign math function 2020-10-12 21:06:19 +09:00
WebAssembly Reland "[WebAssembly] Emulate v128.const efficiently"" 2020-10-13 04:36:59 +00:00
WinCFGuard Reland [CFGuard] Add address-taken IAT tables and delay-load support 2020-10-13 13:20:52 -07:00
WinEH
X86 Revert "Reland "[SCEV] Model ptrtoint(SCEVUnknown) cast not as unknown, but as zext/trunc/self of SCEVUnknown"" and it's follow-ups 2020-10-14 16:09:18 +03:00
XCore