forked from OSchip/llvm-project
6a803f6162
Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018 |
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.. | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile | ||
MipsAsmBackend.cpp | ||
MipsAsmBackend.h | ||
MipsBaseInfo.h | ||
MipsELFObjectWriter.cpp | ||
MipsELFStreamer.cpp | ||
MipsELFStreamer.h | ||
MipsFixupKinds.h | ||
MipsMCAsmInfo.cpp | ||
MipsMCAsmInfo.h | ||
MipsMCCodeEmitter.cpp | ||
MipsMCCodeEmitter.h | ||
MipsMCExpr.cpp | ||
MipsMCExpr.h | ||
MipsMCNaCl.h | ||
MipsMCTargetDesc.cpp | ||
MipsMCTargetDesc.h | ||
MipsNaClELFStreamer.cpp | ||
MipsTargetStreamer.cpp |