forked from OSchip/llvm-project
132 lines
3.8 KiB
LLVM
132 lines
3.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
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; Test various conditions where OptimizeLoopTermCond doesn't look at a
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; memory instruction use and fails to find the address space.
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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; CHECK-LABEL: @local_cmp_user(
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; CHECK: bb11:
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; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 2, %entry ]
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; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
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; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
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; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, -2
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; CHECK: br i1
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; CHECK: bb:
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; CHECK: inttoptr i32 %lsr.iv.next2 to i8 addrspace(3)*
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; CHECK: %c1 = icmp ne i8 addrspace(3)*
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define amdgpu_kernel void @local_cmp_user(i32 %arg0) nounwind {
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entry:
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br label %bb11
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bb11:
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%i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
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%ii = shl i32 %i, 1
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%c0 = icmp eq i32 %i, %arg0
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br i1 %c0, label %bb13, label %bb
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bb:
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%t = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(3)* undef
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%p = getelementptr i8, i8 addrspace(3)* %t, i32 %ii
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%c1 = icmp ne i8 addrspace(3)* %p, null
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%i.next = add i32 %i, 1
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br i1 %c1, label %bb11, label %bb13
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bb13:
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unreachable
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}
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; CHECK-LABEL: @global_cmp_user(
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; CHECK: %lsr.iv1 = phi i64
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; CHECK: %lsr.iv = phi i64
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; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
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; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, -2
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; CHECK: br i1
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; CHECK: bb:
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; CHECK: inttoptr i64 %lsr.iv.next2 to i8 addrspace(1)*
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; CHECK: icmp ne i8 addrspace(1)* %t
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define amdgpu_kernel void @global_cmp_user(i64 %arg0) nounwind {
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entry:
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br label %bb11
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bb11:
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%i = phi i64 [ 0, %entry ], [ %i.next, %bb ]
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%ii = shl i64 %i, 1
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%c0 = icmp eq i64 %i, %arg0
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br i1 %c0, label %bb13, label %bb
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bb:
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%t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef
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%p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii
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%c1 = icmp ne i8 addrspace(1)* %p, null
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%i.next = add i64 %i, 1
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br i1 %c1, label %bb11, label %bb13
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bb13:
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unreachable
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}
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; CHECK-LABEL: @global_gep_user(
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; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 0, %entry ]
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; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
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; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
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; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, 2
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; CHECK: br i1
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; CHECK: bb:
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; CHECK: %idxprom = sext i32 %lsr.iv1 to i64
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; CHECK: getelementptr i8, i8 addrspace(1)* %t, i64 %idxprom
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define amdgpu_kernel void @global_gep_user(i32 %arg0) nounwind {
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entry:
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br label %bb11
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bb11:
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%i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
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%ii = shl i32 %i, 1
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%c0 = icmp eq i32 %i, %arg0
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br i1 %c0, label %bb13, label %bb
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bb:
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%t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef
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%p = getelementptr i8, i8 addrspace(1)* %t, i32 %ii
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%c1 = icmp ne i8 addrspace(1)* %p, null
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%i.next = add i32 %i, 1
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br i1 %c1, label %bb11, label %bb13
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bb13:
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unreachable
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}
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; CHECK-LABEL: @global_sext_scale_user(
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; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 0, %entry ]
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; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
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; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
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; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, 2
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; CHECK: br i1
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; CHECK: bb
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; CHECK: %p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii.ext
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define amdgpu_kernel void @global_sext_scale_user(i32 %arg0) nounwind {
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entry:
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br label %bb11
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bb11:
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%i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
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%ii = shl i32 %i, 1
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%ii.ext = sext i32 %ii to i64
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%c0 = icmp eq i32 %i, %arg0
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br i1 %c0, label %bb13, label %bb
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bb:
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%t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef
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%p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii.ext
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%c1 = icmp ne i8 addrspace(1)* %p, null
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%i.next = add i32 %i, 1
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br i1 %c1, label %bb11, label %bb13
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bb13:
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unreachable
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}
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