forked from OSchip/llvm-project
577 lines
20 KiB
C++
577 lines
20 KiB
C++
//===-- ImplicitNullChecks.cpp - Fold null checks into memory accesses ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass turns explicit null checks of the form
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//
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// test %r10, %r10
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// je throw_npe
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// movl (%r10), %esi
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// ...
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//
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// to
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//
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// faulting_load_op("movl (%r10), %esi", throw_npe)
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// ...
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//
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// With the help of a runtime that understands the .fault_maps section,
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// faulting_load_op branches to throw_npe if executing movl (%r10), %esi incurs
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// a page fault.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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static cl::opt<int> PageSize("imp-null-check-page-size",
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cl::desc("The page size of the target in bytes"),
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cl::init(4096));
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#define DEBUG_TYPE "implicit-null-checks"
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STATISTIC(NumImplicitNullChecks,
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"Number of explicit null checks made implicit");
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namespace {
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class ImplicitNullChecks : public MachineFunctionPass {
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/// Represents one null check that can be made implicit.
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class NullCheck {
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// The memory operation the null check can be folded into.
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MachineInstr *MemOperation;
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// The instruction actually doing the null check (Ptr != 0).
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MachineInstr *CheckOperation;
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// The block the check resides in.
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MachineBasicBlock *CheckBlock;
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// The block branched to if the pointer is non-null.
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MachineBasicBlock *NotNullSucc;
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// The block branched to if the pointer is null.
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MachineBasicBlock *NullSucc;
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// If this is non-null, then MemOperation has a dependency on on this
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// instruction; and it needs to be hoisted to execute before MemOperation.
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MachineInstr *OnlyDependency;
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public:
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explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation,
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MachineBasicBlock *checkBlock,
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MachineBasicBlock *notNullSucc,
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MachineBasicBlock *nullSucc,
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MachineInstr *onlyDependency)
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: MemOperation(memOperation), CheckOperation(checkOperation),
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CheckBlock(checkBlock), NotNullSucc(notNullSucc), NullSucc(nullSucc),
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OnlyDependency(onlyDependency) {}
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MachineInstr *getMemOperation() const { return MemOperation; }
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MachineInstr *getCheckOperation() const { return CheckOperation; }
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MachineBasicBlock *getCheckBlock() const { return CheckBlock; }
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MachineBasicBlock *getNotNullSucc() const { return NotNullSucc; }
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MachineBasicBlock *getNullSucc() const { return NullSucc; }
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MachineInstr *getOnlyDependency() const { return OnlyDependency; }
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};
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const TargetInstrInfo *TII = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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AliasAnalysis *AA = nullptr;
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MachineModuleInfo *MMI = nullptr;
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bool analyzeBlockForNullChecks(MachineBasicBlock &MBB,
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SmallVectorImpl<NullCheck> &NullCheckList);
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MachineInstr *insertFaultingLoad(MachineInstr *LoadMI, MachineBasicBlock *MBB,
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MachineBasicBlock *HandlerMBB);
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void rewriteNullChecks(ArrayRef<NullCheck> NullCheckList);
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public:
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static char ID;
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ImplicitNullChecks() : MachineFunctionPass(ID) {
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initializeImplicitNullChecksPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<AAResultsWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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/// \brief Detect re-ordering hazards and dependencies.
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///
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/// This class keeps track of defs and uses, and can be queried if a given
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/// machine instruction can be re-ordered from after the machine instructions
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/// seen so far to before them.
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class HazardDetector {
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static MachineInstr *getUnknownMI() {
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return DenseMapInfo<MachineInstr *>::getTombstoneKey();
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}
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// Maps physical registers to the instruction defining them. If there has
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// been more than one def of an specific register, that register is mapped to
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// getUnknownMI().
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DenseMap<unsigned, MachineInstr *> RegDefs;
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DenseSet<unsigned> RegUses;
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const TargetRegisterInfo &TRI;
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bool hasSeenClobber;
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AliasAnalysis &AA;
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public:
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explicit HazardDetector(const TargetRegisterInfo &TRI, AliasAnalysis &AA)
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: TRI(TRI), hasSeenClobber(false), AA(AA) {}
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/// \brief Make a note of \p MI for later queries to isSafeToHoist.
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///
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/// May clobber this HazardDetector instance. \see isClobbered.
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void rememberInstruction(MachineInstr *MI);
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/// \brief Return true if it is safe to hoist \p MI from after all the
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/// instructions seen so far (via rememberInstruction) to before it. If \p MI
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/// has one and only one transitive dependency, set \p Dependency to that
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/// instruction. If there are more dependencies, return false.
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bool isSafeToHoist(MachineInstr *MI, MachineInstr *&Dependency);
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/// \brief Return true if this instance of HazardDetector has been clobbered
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/// (i.e. has no more useful information).
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///
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/// A HazardDetecter is clobbered when it sees a construct it cannot
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/// understand, and it would have to return a conservative answer for all
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/// future queries. Having a separate clobbered state lets the client code
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/// bail early, without making queries about all of the future instructions
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/// (which would have returned the most conservative answer anyway).
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///
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/// Calling rememberInstruction or isSafeToHoist on a clobbered HazardDetector
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/// is an error.
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bool isClobbered() { return hasSeenClobber; }
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};
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}
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void HazardDetector::rememberInstruction(MachineInstr *MI) {
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assert(!isClobbered() &&
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"Don't add instructions to a clobbered hazard detector");
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if (MI->mayStore() || MI->hasUnmodeledSideEffects()) {
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hasSeenClobber = true;
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return;
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}
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for (auto *MMO : MI->memoperands()) {
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// Right now we don't want to worry about LLVM's memory model.
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if (!MMO->isUnordered()) {
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hasSeenClobber = true;
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return;
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}
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}
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for (auto &MO : MI->operands()) {
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if (!MO.isReg() || !MO.getReg())
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continue;
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if (MO.isDef()) {
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auto It = RegDefs.find(MO.getReg());
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if (It == RegDefs.end())
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RegDefs.insert({MO.getReg(), MI});
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else {
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assert(It->second && "Found null MI?");
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It->second = getUnknownMI();
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}
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} else
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RegUses.insert(MO.getReg());
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}
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}
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bool HazardDetector::isSafeToHoist(MachineInstr *MI,
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MachineInstr *&Dependency) {
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assert(!isClobbered() && "isSafeToHoist cannot do anything useful!");
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Dependency = nullptr;
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// Right now we don't want to worry about LLVM's memory model. This can be
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// made more precise later.
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for (auto *MMO : MI->memoperands())
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if (!MMO->isUnordered())
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return false;
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for (auto &MO : MI->operands()) {
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if (MO.isReg() && MO.getReg()) {
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for (auto &RegDef : RegDefs) {
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unsigned Reg = RegDef.first;
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MachineInstr *MI = RegDef.second;
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if (!TRI.regsOverlap(Reg, MO.getReg()))
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continue;
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// We found a write-after-write or read-after-write, see if the
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// instruction causing this dependency can be hoisted too.
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if (MI == getUnknownMI())
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// We don't have precise dependency information.
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return false;
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if (Dependency) {
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if (Dependency == MI)
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continue;
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// We already have one dependency, and we can track only one.
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return false;
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}
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// Now check if MI is actually a dependency that can be hoisted.
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// We don't want to track transitive dependencies. We already know that
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// MI is the only instruction that defines Reg, but we need to be sure
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// that it does not use any registers that have been defined (trivially
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// checked below by ensuring that there are no register uses), and that
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// it is the only def for every register it defines (otherwise we could
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// violate a write after write hazard).
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auto IsMIOperandSafe = [&](MachineOperand &MO) {
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if (!MO.isReg() || !MO.getReg())
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return true;
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if (MO.isUse())
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return false;
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assert((!MO.isDef() || RegDefs.count(MO.getReg())) &&
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"All defs must be tracked in RegDefs by now!");
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return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI;
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};
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if (!all_of(MI->operands(), IsMIOperandSafe))
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return false;
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// Now check for speculation safety:
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bool SawStore = true;
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if (!MI->isSafeToMove(&AA, SawStore) || MI->mayLoad())
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return false;
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Dependency = MI;
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}
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if (MO.isDef())
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for (unsigned Reg : RegUses)
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if (TRI.regsOverlap(Reg, MO.getReg()))
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return false; // We found a write-after-read
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}
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}
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return true;
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}
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bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getRegInfo().getTargetRegisterInfo();
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MMI = &MF.getMMI();
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AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
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SmallVector<NullCheck, 16> NullCheckList;
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for (auto &MBB : MF)
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analyzeBlockForNullChecks(MBB, NullCheckList);
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if (!NullCheckList.empty())
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rewriteNullChecks(NullCheckList);
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return !NullCheckList.empty();
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}
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// Return true if any register aliasing \p Reg is live-in into \p MBB.
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static bool AnyAliasLiveIn(const TargetRegisterInfo *TRI,
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MachineBasicBlock *MBB, unsigned Reg) {
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for (MCRegAliasIterator AR(Reg, TRI, /*IncludeSelf*/ true); AR.isValid();
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++AR)
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if (MBB->isLiveIn(*AR))
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return true;
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return false;
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}
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/// Analyze MBB to check if its terminating branch can be turned into an
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/// implicit null check. If yes, append a description of the said null check to
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/// NullCheckList and return true, else return false.
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bool ImplicitNullChecks::analyzeBlockForNullChecks(
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MachineBasicBlock &MBB, SmallVectorImpl<NullCheck> &NullCheckList) {
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typedef TargetInstrInfo::MachineBranchPredicate MachineBranchPredicate;
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MDNode *BranchMD = nullptr;
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if (auto *BB = MBB.getBasicBlock())
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BranchMD = BB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit);
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if (!BranchMD)
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return false;
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MachineBranchPredicate MBP;
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if (TII->analyzeBranchPredicate(MBB, MBP, true))
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return false;
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// Is the predicate comparing an integer to zero?
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if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
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(MBP.Predicate == MachineBranchPredicate::PRED_NE ||
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MBP.Predicate == MachineBranchPredicate::PRED_EQ)))
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return false;
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// If we cannot erase the test instruction itself, then making the null check
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// implicit does not buy us much.
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if (!MBP.SingleUseCondition)
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return false;
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MachineBasicBlock *NotNullSucc, *NullSucc;
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if (MBP.Predicate == MachineBranchPredicate::PRED_NE) {
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NotNullSucc = MBP.TrueDest;
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NullSucc = MBP.FalseDest;
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} else {
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NotNullSucc = MBP.FalseDest;
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NullSucc = MBP.TrueDest;
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}
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// We handle the simplest case for now. We can potentially do better by using
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// the machine dominator tree.
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if (NotNullSucc->pred_size() != 1)
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return false;
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// Starting with a code fragment like:
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//
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// test %RAX, %RAX
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// jne LblNotNull
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//
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// LblNull:
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// callq throw_NullPointerException
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//
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// LblNotNull:
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// Inst0
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// Inst1
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// ...
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// Def = Load (%RAX + <offset>)
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// ...
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//
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//
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// we want to end up with
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//
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// Def = FaultingLoad (%RAX + <offset>), LblNull
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// jmp LblNotNull ;; explicit or fallthrough
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//
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// LblNotNull:
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// Inst0
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// Inst1
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// ...
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//
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// LblNull:
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// callq throw_NullPointerException
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//
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//
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// To see why this is legal, consider the two possibilities:
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//
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// 1. %RAX is null: since we constrain <offset> to be less than PageSize, the
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// load instruction dereferences the null page, causing a segmentation
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// fault.
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//
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// 2. %RAX is not null: in this case we know that the load cannot fault, as
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// otherwise the load would've faulted in the original program too and the
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// original program would've been undefined.
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//
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// This reasoning cannot be extended to justify hoisting through arbitrary
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// control flow. For instance, in the example below (in pseudo-C)
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//
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// if (ptr == null) { throw_npe(); unreachable; }
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// if (some_cond) { return 42; }
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// v = ptr->field; // LD
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// ...
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//
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// we cannot (without code duplication) use the load marked "LD" to null check
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// ptr -- clause (2) above does not apply in this case. In the above program
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// the safety of ptr->field can be dependent on some_cond; and, for instance,
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// ptr could be some non-null invalid reference that never gets loaded from
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// because some_cond is always true.
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unsigned PointerReg = MBP.LHS.getReg();
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HazardDetector HD(*TRI, *AA);
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for (auto MII = NotNullSucc->begin(), MIE = NotNullSucc->end(); MII != MIE;
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++MII) {
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MachineInstr &MI = *MII;
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unsigned BaseReg;
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int64_t Offset;
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MachineInstr *Dependency = nullptr;
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if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
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if (MI.mayLoad() && !MI.isPredicable() && BaseReg == PointerReg &&
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Offset < PageSize && MI.getDesc().getNumDefs() <= 1 &&
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HD.isSafeToHoist(&MI, Dependency)) {
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auto DependencyOperandIsOk = [&](MachineOperand &MO) {
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assert(!(MO.isReg() && MO.isUse()) &&
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"No transitive dependendencies please!");
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if (!MO.isReg() || !MO.getReg() || !MO.isDef())
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return true;
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// Make sure that we won't clobber any live ins to the sibling block
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// by hoisting Dependency. For instance, we can't hoist INST to
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// before the null check (even if it safe, and does not violate any
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// dependencies in the non_null_block) if %rdx is live in to
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// _null_block.
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//
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// test %rcx, %rcx
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// je _null_block
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// _non_null_block:
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// %rdx<def> = INST
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// ...
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if (AnyAliasLiveIn(TRI, NullSucc, MO.getReg()))
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return false;
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// Make sure Dependency isn't re-defining the base register. Then we
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// won't get the memory operation on the address we want.
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if (TRI->regsOverlap(MO.getReg(), BaseReg))
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return false;
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return true;
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};
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bool DependencyOperandsAreOk =
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!Dependency ||
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all_of(Dependency->operands(), DependencyOperandIsOk);
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if (DependencyOperandsAreOk) {
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NullCheckList.emplace_back(&MI, MBP.ConditionDef, &MBB, NotNullSucc,
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NullSucc, Dependency);
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return true;
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}
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}
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HD.rememberInstruction(&MI);
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if (HD.isClobbered())
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return false;
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}
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return false;
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}
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/// Wrap a machine load instruction, LoadMI, into a FAULTING_LOAD_OP machine
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/// instruction. The FAULTING_LOAD_OP instruction does the same load as LoadMI
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/// (defining the same register), and branches to HandlerMBB if the load
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/// faults. The FAULTING_LOAD_OP instruction is inserted at the end of MBB.
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MachineInstr *
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ImplicitNullChecks::insertFaultingLoad(MachineInstr *LoadMI,
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MachineBasicBlock *MBB,
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MachineBasicBlock *HandlerMBB) {
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const unsigned NoRegister = 0; // Guaranteed to be the NoRegister value for
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// all targets.
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DebugLoc DL;
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unsigned NumDefs = LoadMI->getDesc().getNumDefs();
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assert(NumDefs <= 1 && "other cases unhandled!");
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unsigned DefReg = NoRegister;
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if (NumDefs != 0) {
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DefReg = LoadMI->defs().begin()->getReg();
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assert(std::distance(LoadMI->defs().begin(), LoadMI->defs().end()) == 1 &&
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"expected exactly one def!");
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}
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auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg)
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.addMBB(HandlerMBB)
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.addImm(LoadMI->getOpcode());
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for (auto &MO : LoadMI->uses())
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MIB.addOperand(MO);
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MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end());
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return MIB;
|
|
}
|
|
|
|
/// Rewrite the null checks in NullCheckList into implicit null checks.
|
|
void ImplicitNullChecks::rewriteNullChecks(
|
|
ArrayRef<ImplicitNullChecks::NullCheck> NullCheckList) {
|
|
DebugLoc DL;
|
|
|
|
for (auto &NC : NullCheckList) {
|
|
// Remove the conditional branch dependent on the null check.
|
|
unsigned BranchesRemoved = TII->RemoveBranch(*NC.getCheckBlock());
|
|
(void)BranchesRemoved;
|
|
assert(BranchesRemoved > 0 && "expected at least one branch!");
|
|
|
|
if (auto *DepMI = NC.getOnlyDependency()) {
|
|
DepMI->removeFromParent();
|
|
NC.getCheckBlock()->insert(NC.getCheckBlock()->end(), DepMI);
|
|
}
|
|
|
|
// Insert a faulting load where the conditional branch was originally. We
|
|
// check earlier ensures that this bit of code motion is legal. We do not
|
|
// touch the successors list for any basic block since we haven't changed
|
|
// control flow, we've just made it implicit.
|
|
MachineInstr *FaultingLoad = insertFaultingLoad(
|
|
NC.getMemOperation(), NC.getCheckBlock(), NC.getNullSucc());
|
|
// Now the values defined by MemOperation, if any, are live-in of
|
|
// the block of MemOperation.
|
|
// The original load operation may define implicit-defs alongside
|
|
// the loaded value.
|
|
MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
|
|
for (const MachineOperand &MO : FaultingLoad->operands()) {
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!Reg || MBB->isLiveIn(Reg))
|
|
continue;
|
|
MBB->addLiveIn(Reg);
|
|
}
|
|
|
|
if (auto *DepMI = NC.getOnlyDependency()) {
|
|
for (auto &MO : DepMI->operands()) {
|
|
if (!MO.isReg() || !MO.getReg() || !MO.isDef())
|
|
continue;
|
|
if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
|
|
NC.getNotNullSucc()->addLiveIn(MO.getReg());
|
|
}
|
|
}
|
|
|
|
NC.getMemOperation()->eraseFromParent();
|
|
NC.getCheckOperation()->eraseFromParent();
|
|
|
|
// Insert an *unconditional* branch to not-null successor.
|
|
TII->InsertBranch(*NC.getCheckBlock(), NC.getNotNullSucc(), nullptr,
|
|
/*Cond=*/None, DL);
|
|
|
|
NumImplicitNullChecks++;
|
|
}
|
|
}
|
|
|
|
char ImplicitNullChecks::ID = 0;
|
|
char &llvm::ImplicitNullChecksID = ImplicitNullChecks::ID;
|
|
INITIALIZE_PASS_BEGIN(ImplicitNullChecks, "implicit-null-checks",
|
|
"Implicit null checks", false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
|
|
INITIALIZE_PASS_END(ImplicitNullChecks, "implicit-null-checks",
|
|
"Implicit null checks", false, false)
|