forked from OSchip/llvm-project
274d72faad
The ARM/ARM64 AESE and AESD instructions have a builtin XOR as the first step in the instruction. Therefore, if the AES key is zero and the AES data was previously XORed, it can be combined into a single instruction. Differential Revision: https://reviews.llvm.org/D47239 Patch by Michael Brase! llvm-svn: 333193 |
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CMakeLists.txt | ||
InstCombineAddSub.cpp | ||
InstCombineAndOrXor.cpp | ||
InstCombineCalls.cpp | ||
InstCombineCasts.cpp | ||
InstCombineCompares.cpp | ||
InstCombineInternal.h | ||
InstCombineLoadStoreAlloca.cpp | ||
InstCombineMulDivRem.cpp | ||
InstCombinePHI.cpp | ||
InstCombineSelect.cpp | ||
InstCombineShifts.cpp | ||
InstCombineSimplifyDemanded.cpp | ||
InstCombineVectorOps.cpp | ||
InstructionCombining.cpp | ||
LLVMBuild.txt |