forked from OSchip/llvm-project
220 lines
6.9 KiB
C++
220 lines
6.9 KiB
C++
//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "SIMachineFunctionInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#define MAX_LANES 64
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using namespace llvm;
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// Pin the vtable to this file.
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void SIMachineFunctionInfo::anchor() {}
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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TIDReg(AMDGPU::NoRegister),
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ScratchRSrcReg(AMDGPU::NoRegister),
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ScratchWaveOffsetReg(AMDGPU::NoRegister),
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PrivateSegmentBufferUserSGPR(AMDGPU::NoRegister),
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DispatchPtrUserSGPR(AMDGPU::NoRegister),
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QueuePtrUserSGPR(AMDGPU::NoRegister),
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KernargSegmentPtrUserSGPR(AMDGPU::NoRegister),
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DispatchIDUserSGPR(AMDGPU::NoRegister),
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FlatScratchInitUserSGPR(AMDGPU::NoRegister),
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PrivateSegmentSizeUserSGPR(AMDGPU::NoRegister),
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GridWorkGroupCountXUserSGPR(AMDGPU::NoRegister),
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GridWorkGroupCountYUserSGPR(AMDGPU::NoRegister),
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GridWorkGroupCountZUserSGPR(AMDGPU::NoRegister),
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WorkGroupIDXSystemSGPR(AMDGPU::NoRegister),
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WorkGroupIDYSystemSGPR(AMDGPU::NoRegister),
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WorkGroupIDZSystemSGPR(AMDGPU::NoRegister),
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WorkGroupInfoSystemSGPR(AMDGPU::NoRegister),
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PrivateSegmentWaveByteOffsetSystemSGPR(AMDGPU::NoRegister),
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PSInputAddr(0),
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ReturnsVoid(true),
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MaximumWorkGroupSize(0),
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DebuggerReserveTrapVGPRCount(0),
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LDSWaveSpillSize(0),
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PSInputEna(0),
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NumUserSGPRs(0),
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NumSystemSGPRs(0),
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HasSpilledSGPRs(false),
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HasSpilledVGPRs(false),
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HasNonSpillStackObjects(false),
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HasFlatInstructions(false),
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PrivateSegmentBuffer(false),
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DispatchPtr(false),
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QueuePtr(false),
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DispatchID(false),
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KernargSegmentPtr(false),
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FlatScratchInit(false),
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GridWorkgroupCountX(false),
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GridWorkgroupCountY(false),
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GridWorkgroupCountZ(false),
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WorkGroupIDX(false),
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WorkGroupIDY(false),
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WorkGroupIDZ(false),
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WorkGroupInfo(false),
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PrivateSegmentWaveByteOffset(false),
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WorkItemIDX(false),
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WorkItemIDY(false),
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WorkItemIDZ(false) {
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const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
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const Function *F = MF.getFunction();
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PSInputAddr = AMDGPU::getInitialPSInputAddr(*F);
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const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
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if (!AMDGPU::isShader(F->getCallingConv())) {
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KernargSegmentPtr = true;
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WorkGroupIDX = true;
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WorkItemIDX = true;
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}
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if (F->hasFnAttribute("amdgpu-work-group-id-y"))
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WorkGroupIDY = true;
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if (F->hasFnAttribute("amdgpu-work-group-id-z"))
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WorkGroupIDZ = true;
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if (F->hasFnAttribute("amdgpu-work-item-id-y"))
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WorkItemIDY = true;
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if (F->hasFnAttribute("amdgpu-work-item-id-z"))
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WorkItemIDZ = true;
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// X, XY, and XYZ are the only supported combinations, so make sure Y is
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// enabled if Z is.
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if (WorkItemIDZ)
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WorkItemIDY = true;
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bool MaySpill = ST.isVGPRSpillingEnabled(*F);
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bool HasStackObjects = FrameInfo->hasStackObjects();
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if (HasStackObjects || MaySpill)
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PrivateSegmentWaveByteOffset = true;
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if (ST.isAmdHsaOS()) {
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if (HasStackObjects || MaySpill)
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PrivateSegmentBuffer = true;
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if (F->hasFnAttribute("amdgpu-dispatch-ptr"))
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DispatchPtr = true;
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if (F->hasFnAttribute("amdgpu-queue-ptr"))
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QueuePtr = true;
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}
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// We don't need to worry about accessing spills with flat instructions.
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// TODO: On VI where we must use flat for global, we should be able to omit
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// this if it is never used for generic access.
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if (HasStackObjects && ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS &&
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ST.isAmdHsaOS())
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FlatScratchInit = true;
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if (AMDGPU::isCompute(F->getCallingConv()))
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MaximumWorkGroupSize = AMDGPU::getMaximumWorkGroupSize(*F);
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else
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MaximumWorkGroupSize = ST.getWavefrontSize();
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if (ST.debuggerReserveTrapVGPRs())
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DebuggerReserveTrapVGPRCount = 4;
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}
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unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
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const SIRegisterInfo &TRI) {
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PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
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NumUserSGPRs += 4;
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return PrivateSegmentBufferUserSGPR;
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}
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unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
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DispatchPtrUserSGPR = TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
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NumUserSGPRs += 2;
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return DispatchPtrUserSGPR;
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}
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unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
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QueuePtrUserSGPR = TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
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NumUserSGPRs += 2;
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return QueuePtrUserSGPR;
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}
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unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
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KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
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NumUserSGPRs += 2;
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return KernargSegmentPtrUserSGPR;
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}
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unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
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FlatScratchInitUserSGPR = TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
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NumUserSGPRs += 2;
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return FlatScratchInitUserSGPR;
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}
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SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
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MachineFunction *MF,
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unsigned FrameIndex,
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unsigned SubIdx) {
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MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
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MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
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MachineRegisterInfo &MRI = MF->getRegInfo();
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int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
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Offset += SubIdx * 4;
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unsigned LaneVGPRIdx = Offset / (64 * 4);
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unsigned Lane = (Offset / 4) % 64;
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struct SpilledReg Spill;
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Spill.Lane = Lane;
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if (!LaneVGPRs.count(LaneVGPRIdx)) {
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unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
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if (LaneVGPR == AMDGPU::NoRegister)
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// We have no VGPRs left for spilling SGPRs.
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return Spill;
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LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
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BI != BE; ++BI) {
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BI->addLiveIn(LaneVGPR);
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}
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}
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Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
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return Spill;
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}
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unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
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const MachineFunction &MF) const {
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return MaximumWorkGroupSize;
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}
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