forked from OSchip/llvm-project
340 lines
10 KiB
LLVM
340 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; Given pattern:
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; (x shiftopcode Q) shiftopcode K
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; we should rewrite it as
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; x shiftopcode (Q+K) iff (Q+K) u< bitwidth(x)
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; This is valid for any shift, but they must be identical.
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; THIS FOLD DOES *NOT* REQUIRE ANY 'exact'/'nuw'/`nsw` FLAGS!
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; Basic scalar test
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define i32 @t0(i32 %x, i32 %y) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = lshr i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = lshr exact i32 %t1, %t2 ; while there, test that we don't propagate partial 'exact' flag
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ret i32 %t3
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}
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define <2 x i32> @t1_vec_splat(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 30, i32 30>
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%t0 = sub <2 x i32> <i32 32, i32 32>, %y
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%t1 = lshr <2 x i32> %x, %t0
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%t2 = add <2 x i32> %y, <i32 -2, i32 -2>
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%t3 = lshr <2 x i32> %t1, %t2
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ret <2 x i32> %t3
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}
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define <2 x i32> @t2_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @t2_vec_nonsplat(
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; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 30, i32 30>
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%t0 = sub <2 x i32> <i32 32, i32 30>, %y
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%t1 = lshr <2 x i32> %x, %t0
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%t2 = add <2 x i32> %y, <i32 -2, i32 0>
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%t3 = lshr <2 x i32> %t1, %t2
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ret <2 x i32> %t3
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}
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; Basic vector tests
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define <3 x i32> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t3_vec_nonsplat_undef0(
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; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 30, i32 undef, i32 30>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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%t0 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %y
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%t1 = lshr <3 x i32> %x, %t0
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%t2 = add <3 x i32> %y, <i32 -2, i32 -2, i32 -2>
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%t3 = lshr <3 x i32> %t1, %t2
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ret <3 x i32> %t3
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}
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define <3 x i32> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t4_vec_nonsplat_undef1(
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; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 30, i32 undef, i32 30>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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%t0 = sub <3 x i32> <i32 32, i32 32, i32 32>, %y
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%t1 = lshr <3 x i32> %x, %t0
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%t2 = add <3 x i32> %y, <i32 -2, i32 undef, i32 -2>
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%t3 = lshr <3 x i32> %t1, %t2
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ret <3 x i32> %t3
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}
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define <3 x i32> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t5_vec_nonsplat_undef1(
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; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 30, i32 undef, i32 30>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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%t0 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %y
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%t1 = lshr <3 x i32> %x, %t0
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%t2 = add <3 x i32> %y, <i32 -2, i32 undef, i32 -2>
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%t3 = lshr <3 x i32> %t1, %t2
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ret <3 x i32> %t3
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}
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; Some other shift opcodes
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define i32 @t6_shl(i32 %x, i32 %y) {
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; CHECK-LABEL: @t6_shl(
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = shl nuw i32 %x, %t0 ; while there, test that we don't propagate partial 'nuw' flag
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%t2 = add i32 %y, -2
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%t3 = shl nsw i32 %t1, %t2 ; while there, test that we don't propagate partial 'nsw' flag
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ret i32 %t3
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}
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define i32 @t7_ashr(i32 %x, i32 %y) {
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; CHECK-LABEL: @t7_ashr(
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; CHECK-NEXT: [[T3:%.*]] = ashr i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = ashr exact i32 %x, %t0 ; while there, test that we don't propagate partial 'exact' flag
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%t2 = add i32 %y, -2
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%t3 = ashr i32 %t1, %t2
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ret i32 %t3
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}
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; If the same flag is present on both shifts, it can be kept.
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define i32 @t8_lshr_exact_flag_preservation(i32 %x, i32 %y) {
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; CHECK-LABEL: @t8_lshr_exact_flag_preservation(
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; CHECK-NEXT: [[T3:%.*]] = lshr exact i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = lshr exact i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = lshr exact i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @t9_ashr_exact_flag_preservation(i32 %x, i32 %y) {
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; CHECK-LABEL: @t9_ashr_exact_flag_preservation(
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; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = ashr exact i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = ashr exact i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @t10_shl_nuw_flag_preservation(i32 %x, i32 %y) {
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; CHECK-LABEL: @t10_shl_nuw_flag_preservation(
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; CHECK-NEXT: [[T3:%.*]] = shl nuw i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = shl nuw i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = shl nuw nsw i32 %t1, %t2 ; only 'nuw' should be propagated.
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ret i32 %t3
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}
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define i32 @t11_shl_nsw_flag_preservation(i32 %x, i32 %y) {
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; CHECK-LABEL: @t11_shl_nsw_flag_preservation(
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; CHECK-NEXT: [[T3:%.*]] = shl nsw i32 [[X:%.*]], 30
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = shl nsw i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = shl nsw nuw i32 %t1, %t2 ; only 'nuw' should be propagated.
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ret i32 %t3
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}
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; Reduced from https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15587
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@X = external global i32
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define i64 @constantexpr() {
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; CHECK-LABEL: @constantexpr(
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; CHECK-NEXT: ret i64 0
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;
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%A = alloca i64
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%L = load i64, i64* %A
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%V = add i64 ptrtoint (i32* @X to i64), 0
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%B2 = shl i64 %V, 0
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%B4 = ashr i64 %B2, %L
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%B = and i64 undef, %B4
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ret i64 %B
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}
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; No one-use tests since we will only produce a single instruction here.
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; Negative tests
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; Can't fold, total shift would be 32
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define i32 @n12(i32 %x, i32 %y) {
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; CHECK-LABEL: @n12(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 30, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], 2
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; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 30, %y
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%t1 = lshr i32 %x, %t0
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%t2 = add i32 %y, 2
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%t3 = lshr i32 %t1, %t2
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ret i32 %t3
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}
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; Can't fold, for second channel the shift would 32
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define <2 x i32> @t13_vec(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @t13_vec(
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; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 30>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[Y]], <i32 -2, i32 2>
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; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[T1]], [[T2]]
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%t0 = sub <2 x i32> <i32 32, i32 30>, %y
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%t1 = lshr <2 x i32> %x, %t0
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%t2 = add <2 x i32> %y, <i32 -2, i32 2>
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%t3 = lshr <2 x i32> %t1, %t2
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ret <2 x i32> %t3
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}
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; If we have different right-shifts, in general, we can't do anything with it.
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define i32 @n13(i32 %x, i32 %y) {
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; CHECK-LABEL: @n13(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -2
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; CHECK-NEXT: [[T3:%.*]] = ashr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = lshr i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = ashr i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @n14(i32 %x, i32 %y) {
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; CHECK-LABEL: @n14(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -1
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; CHECK-NEXT: [[T3:%.*]] = ashr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = lshr i32 %x, %t0
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%t2 = add i32 %y, -1
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%t3 = ashr i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @n15(i32 %x, i32 %y) {
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; CHECK-LABEL: @n15(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -2
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; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = ashr i32 %x, %t0
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%t2 = add i32 %y, -2
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%t3 = lshr i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @n16(i32 %x, i32 %y) {
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; CHECK-LABEL: @n16(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -1
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; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = ashr i32 %x, %t0
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%t2 = add i32 %y, -1
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%t3 = lshr i32 %t1, %t2
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ret i32 %t3
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}
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; If the shift direction is different, then this should be handled elsewhere.
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define i32 @n17(i32 %x, i32 %y) {
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; CHECK-LABEL: @n17(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -1
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; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = shl i32 %x, %t0
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%t2 = add i32 %y, -1
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%t3 = lshr i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @n18(i32 %x, i32 %y) {
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; CHECK-LABEL: @n18(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -1
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; CHECK-NEXT: [[T3:%.*]] = ashr i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = shl i32 %x, %t0
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%t2 = add i32 %y, -1
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%t3 = ashr i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @n19(i32 %x, i32 %y) {
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; CHECK-LABEL: @n19(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -1
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = lshr i32 %x, %t0
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%t2 = add i32 %y, -1
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%t3 = shl i32 %t1, %t2
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ret i32 %t3
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}
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define i32 @n20(i32 %x, i32 %y) {
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; CHECK-LABEL: @n20(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -1
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = sub i32 32, %y
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%t1 = ashr i32 %x, %t0
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%t2 = add i32 %y, -1
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%t3 = shl i32 %t1, %t2
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ret i32 %t3
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}
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; See https://bugs.llvm.org/show_bug.cgi?id=44802
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define i3 @pr44802(i3 %t0) {
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; CHECK-LABEL: @pr44802(
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; CHECK-NEXT: [[T1:%.*]] = sub i3 0, [[T0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = icmp ne i3 [[T0]], 0
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; CHECK-NEXT: [[T3:%.*]] = zext i1 [[T2]] to i3
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; CHECK-NEXT: [[T4:%.*]] = lshr i3 [[T1]], [[T3]]
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; CHECK-NEXT: [[T5:%.*]] = lshr i3 [[T4]], [[T3]]
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; CHECK-NEXT: ret i3 [[T5]]
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;
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%t1 = sub i3 0, %t0
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%t2 = icmp ne i3 %t0, 0
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%t3 = zext i1 %t2 to i3
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%t4 = lshr i3 %t1, %t3
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%t5 = lshr i3 %t4, %t3
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ret i3 %t5
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}
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