forked from OSchip/llvm-project
cddb0dbcef
This patch implements the handling for the R_PPC64_PCREL_OPT relocation as well as the GOT relocation for the associated R_PPC64_GOT_PCREL34 relocation. On Power10 targets with PC-Relative addressing, the linker can relax GOT-relative accesses to PC-Relative under some conditions. Since the sequence consists of a prefixed load, followed by a non-prefixed access (load or store), the linker needs to replace the first instruction (as the replacement instruction will be prefixed). The compiler communicates to the linker that this optimization is safe by placing the two aforementioned relocations on the GOT load (of the address). The linker then does two things: - Convert the load from the got into a PC-Relative add to compute the address relative to the PC - Find the instruction referred to by the second relocation (R_PPC64_PCREL_OPT) and replace the first with the PC-Relative version of it It is important to synchronize the mapping from legacy memory instructions to their PC-Relative form. Hence, this patch adds a file to be included by both the compiler and the linker so they're always in agreement. Differential revision: https://reviews.llvm.org/D84360 |
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| .. | ||
| AArch64.cpp | ||
| AMDGPU.cpp | ||
| ARM.cpp | ||
| AVR.cpp | ||
| Hexagon.cpp | ||
| MSP430.cpp | ||
| Mips.cpp | ||
| MipsArchTree.cpp | ||
| PPC.cpp | ||
| PPC64.cpp | ||
| PPCInsns.def | ||
| RISCV.cpp | ||
| SPARCV9.cpp | ||
| X86.cpp | ||
| X86_64.cpp | ||