llvm-project/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

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# RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s
--- |
define void @test_add_s32() { ret void }
...
---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_ADD %0, %1
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...