Anton Afanasyev ca9aff9353 [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub) ... Try to use 64-bit SLP vectorization. In addition to horizontal instrs this change triggers optimizations for partial vector operations (for instance, using low halfs of 128-bit registers xmm0 and xmm1 to multiply <2 x float> by <2 x float>). Fixes llvm.org/PR32433 llvm-svn: 353923		2019-02-13 08:26:43 +00:00
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AArch64	Update GettingStarted guide to recommend that people use the new	2019-01-14 22:27:32 +00:00
AMDGPU	Fix vectorization of canonicalize	2018-09-17 13:24:30 +00:00
ARM	[SLP]Update test checks for the SPL vectorizer, NFC.	2019-01-11 20:21:14 +00:00
NVPTX	[SLP]Moved NVPTX test under NVPTX directory, NFC.	2019-01-11 20:42:48 +00:00
PowerPC	[PowerPC] Update Vector Costs for P9	2019-01-26 01:18:48 +00:00
SystemZ	[SLPVectorizer] Add tests related to PR30787, NFCI.	2018-03-29 18:57:03 +00:00
X86	[X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)	2019-02-13 08:26:43 +00:00
XCore	[SLP]Update test checks for the SPL vectorizer, NFC.	2019-01-11 20:21:14 +00:00
int_sideeffect.ll	[SLP]Update test checks for the SPL vectorizer, NFC.	2019-01-11 20:21:14 +00:00