forked from OSchip/llvm-project
90 lines
1.8 KiB
LLVM
90 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s
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; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
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target triple = "hexagon"
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@Enum_global = external global i8
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define i32 @Func_3(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp eq i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3b(i32) nounwind readonly {
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entry:
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; CHECK-NOT: mux
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%1 = load i8, i8* @Enum_global, align 1
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%2 = trunc i32 %0 to i8
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%cmp = icmp ne i8 %1, %2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3c(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp eq i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3d(i32) nounwind readonly {
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entry:
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; CHECK-NOT: mux
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%1 = load i8, i8* @Enum_global, align 1
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%2 = trunc i32 %0 to i8
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%cmp = icmp eq i8 %1, %2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3e(i32) nounwind readonly {
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entry:
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; CHECK-NOT: mux
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%1 = load i8, i8* @Enum_global, align 1
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%2 = trunc i32 %0 to i8
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%cmp = icmp eq i8 %1, %2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3f(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp ugt i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3g(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp ult i32 %conv, 3
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3h(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 254
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%cmp = icmp ult i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3i(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 254
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%cmp = icmp ugt i32 %conv, 1
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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