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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 3ae03f67fe [RISCV] Add helper function to share some of the code for isel of vector load/store intrinsics. 
Many of the operands are handled the same or in the same order
for all these intrinsics. Factor out the code for selecting and
pushing them into the Operands vector.

Differential Revision: https://reviews.llvm.org/D99923
 		2021-04-06 09:54:24 -07:00
..
AsmParser [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
Disassembler [RISCV] Fix shared libs build 2021-02-09 06:14:25 -06:00
MCTargetDesc [RISCV] Improve 64-bit integer constant materialization for more cases. 2021-04-02 10:18:08 -07:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
CMakeLists.txt [RISCV] Merge Utils library into MCTargetDesc 2021-01-14 11:47:30 -08:00
RISCV.h [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCV.td [RISCV] Fix name of Zba extension (NFC) 2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCVCallLowering.cpp [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallLowering.h [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
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RISCVCleanupVSETVLI.cpp [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVFrameLowering.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
RISCVFrameLowering.h [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
RISCVISelDAGToDAG.cpp [RISCV] Add helper function to share some of the code for isel of vector load/store intrinsics. 2021-04-06 09:54:24 -07:00
RISCVISelDAGToDAG.h [RISCV] Add helper function to share some of the code for isel of vector load/store intrinsics. 2021-04-06 09:54:24 -07:00
RISCVISelLowering.cpp [RISCV] Split RISCVISD::VMV_S_XF_VL into separate integer and FP. 2021-04-05 12:57:35 -07:00
RISCVISelLowering.h [RISCV] Split RISCVISD::VMV_S_XF_VL into separate integer and FP. 2021-04-05 12:57:35 -07:00
RISCVInstrFormats.td [RISCV] Make scalable vector FMA commutable for register allocation. 2021-02-08 10:05:33 -08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
RISCVInstrInfo.h [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVInstrInfo.td [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
RISCVInstrInfoA.td [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode. 2021-03-08 09:06:56 -08:00
RISCVInstrInfoB.td [RISCV] Lower orc.b intrinsic to RISCVISD::GORCI. 2021-04-04 12:31:41 -07:00
RISCVInstrInfoC.td [RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg. 2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVInstrInfoF.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVInstrInfoM.td [RISCV] Add custom type legalization to form MULHSU when possible. 2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate 2021-03-31 09:26:41 -07:00
RISCVInstrInfoVPseudos.td [RISCV] Add isel patterns to handle vrsub intrinsic with 2 vector operands. 2021-04-01 14:10:21 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Lower scalable vector masked loads to intrinsics to match fixed vectors and reduce isel patterns. 2021-03-19 10:39:35 -07:00
RISCVInstrInfoVVLPatterns.td [RISCV] Add SDTCisInt to the SDTRVVSlide1 since it is only used for vslide1up.vx/vslide1down.vx. 2021-04-05 13:03:39 -07:00
RISCVInstrInfoZfh.td [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 2021-03-26 16:37:20 -07:00
RISCVInstructionSelector.cpp RISCV: Avoid GlobalISel build break in a future patch 2020-07-13 14:01:57 -04:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCVMachineFunctionInfo.h [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
RISCVMergeBaseOffset.cpp [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp [RISCV] remove redundant instruction when eliminate frame index 2021-03-21 18:54:00 +08:00
RISCVRegisterInfo.h [RISCV] Improve register allocation around vector masks 2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td [RISCV] Support inline asm for vector instructions. 2021-03-15 11:02:18 +08:00
RISCVSchedRocket.td [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC 2021-03-31 15:06:14 -07:00
RISCVSchedSiFive7.td [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC 2021-03-31 15:06:14 -07:00
RISCVSchedule.td [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC 2021-03-31 15:06:14 -07:00
RISCVScheduleB.td [RISCV] Move scheduling resources for B into a separate file (NFC) 2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp [RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple. 2021-03-14 17:21:31 -07:00
RISCVSubtarget.h [RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other. 2021-02-09 10:47:23 -08:00
RISCVSystemOperands.td [RISCV] Enable the use of the old mucounteren name 2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. 2021-03-02 12:55:51 -08:00
RISCVTargetMachine.h [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. 2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects 2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [RISCV] Reorder checks in RISCVTTIImpl::getGatherScatterOpCost to avoid calling getMinRVVVectorSizeInBits() when V extension is not enabled. 2021-03-25 14:20:47 -07:00
RISCVTargetTransformInfo.h [RISCV] Add basic cost modelling for fixed vector gather/scatter. 2021-03-24 11:14:14 -07:00