llvm-project

History

Matt Arsenault 4bd7236193 AMDGPU: Fix handling of 16-bit immediates Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. llvm-svn: 289306		2016-12-10 00:39:12 +00:00
..
AArch64	Move .mir tests to appropriate directories	2016-12-09 19:08:15 +00:00
AMDGPU	AMDGPU: Fix handling of 16-bit immediates	2016-12-10 00:39:12 +00:00
ARM	Move .mir tests to appropriate directories	2016-12-09 19:08:15 +00:00
Generic	[MIRPrinter] XFAIL test for powerpc	2016-11-18 20:08:05 +00:00
Hexagon	Move .mir tests to appropriate directories	2016-12-09 19:08:15 +00:00
Mips	MIRParser: Use shorter cfi identifiers	2016-07-26 18:20:00 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	[MIRPrinter] Print raw branch probabilities as expected by MIRParser	2016-11-18 19:37:24 +00:00
README	Add README describing the intention of test/CodeGen/MIR	2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.