llvm-project/llvm/test/MC/Disassembler
Thomas Lively 22442924a8 [WebAssembly] v128.const
Summary:
This CL implements v128.const for each vector type. New operand types
are added to ensure the vector contents can be serialized without LEB
encoding. Tests are added for instruction selection, encoding,
assembly and disassembly.

Reviewers: aheejin, dschuff, aardappel

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50873

llvm-svn: 340336
2018-08-21 21:03:18 +00:00
..
AArch64 [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
AMDGPU AMDGPU: Fix v_dot{4, 8}* instruction encoding 2018-05-15 19:32:47 +00:00
ARC [ARC] Add LImm support for J/JL 2018-04-13 15:10:34 +00:00
ARM [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
Hexagon NFC - Various typo fixes in tests 2018-07-04 13:28:39 +00:00
Lanai
Mips [mips] Correct the predicates of arithmetic and logic instructions. 2018-05-30 11:33:35 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly [WebAssembly] v128.const 2018-08-21 21:03:18 +00:00
X86 [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. 2018-08-13 22:06:28 +00:00
XCore