llvm-project/llvm/test/MC
Thomas Lively 22442924a8 [WebAssembly] v128.const
Summary:
This CL implements v128.const for each vector type. New operand types
are added to ensure the vector contents can be serialized without LEB
encoding. Tests are added for instruction selection, encoding,
assembly and disassembly.

Reviewers: aheejin, dschuff, aardappel

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50873

llvm-svn: 340336
2018-08-21 21:03:18 +00:00
..
AArch64 [AArch64][SVE] Asm: Add SVE System registers 2018-08-20 09:16:59 +00:00
AMDGPU [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
ARM [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
AVR [AVR] Implement some missing code paths 2017-12-11 11:01:27 +00:00
AsmParser [AsmParser] Fix preserve-comments-crlf.s on FreeBSD 2018-07-26 06:07:03 +00:00
BPF bpf: New disassembler testcases for 32-bit subregister support 2018-02-23 23:49:35 +00:00
COFF [MC] Improve COFF associative section lookup 2018-08-16 21:34:41 +00:00
Disassembler [WebAssembly] v128.const 2018-08-21 21:03:18 +00:00
ELF [DWARF] Unclamp line table version on Darwin for v5 and later. 2018-08-08 21:16:50 +00:00
Hexagon Check for tied operands 2018-08-13 14:01:25 +00:00
Lanai
MachO [MC] Error on a .zerofill directive in a non-virtual section 2018-07-02 17:29:43 +00:00
Mips [mips] Replace custom parsing logic for data directives by the `addAliasForDirective` 2018-07-25 07:07:43 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
RISCV [RISC-V] Fixed alias for addi x2, x2, 0 2018-08-09 20:51:53 +00:00
Sparc [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
SystemZ [SystemZ, AsmParser] Enable the mnemonic spell corrector. 2017-07-18 09:17:00 +00:00
WebAssembly [WebAssembly] v128.const 2018-08-21 21:03:18 +00:00
X86 [MC][X86] Enhance X86 Register expression handling to more closely match GCC. 2018-08-16 16:31:14 +00:00