forked from OSchip/llvm-project
55 lines
1.7 KiB
YAML
55 lines
1.7 KiB
YAML
# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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# REQUIRES: global-isel, aarch64-registered-target
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test() { ret void }
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...
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---
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name: test
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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%0(s64) = COPY $x0
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%1(<4 x s16>) = COPY $x0
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; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
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; CHECK: instruction: %2:gpr(s64) = G_SEXT_INREG
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%2(s64) = G_SEXT_INREG %0, %0
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; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
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; CHECK: instruction: %3:gpr(s64) = G_SEXT_INREG
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%3(s64) = G_SEXT_INREG %0, i8 8
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; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
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; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
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; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
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; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
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%4(<2 x s32>) = G_SEXT_INREG %0, 8
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; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
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; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
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%5(<2 x s32>) = G_SEXT_INREG %1, 8
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; CHECK: *** Bad machine code: G_SEXT_INREG size must be >= 1 ***
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; CHECK: instruction: %6:gpr(s64) = G_SEXT_INREG
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%6(s64) = G_SEXT_INREG %0, 0
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; CHECK: *** Bad machine code: G_SEXT_INREG size must be less than source bit width ***
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; CHECK: instruction: %7:gpr(s64) = G_SEXT_INREG
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%7(s64) = G_SEXT_INREG %0, 128
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...
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