forked from OSchip/llvm-project
148 lines
4.1 KiB
LLVM
148 lines
4.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
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;
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;
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; Most SALU instructions ignore control flow, so we need to make sure
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; they don't overwrite values from other blocks.
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; If the branch decision is made based on a value in an SGPR then all
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; threads will execute the same code paths, so we don't need to worry
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; about instructions in different blocks overwriting each other.
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; SI-LABEL: {{^}}sgpr_if_else_salu_br:
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; SI: s_add
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; SI: s_branch
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; SI: s_sub
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define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = sub i32 %b, %c
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br label %endif
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else:
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%2 = add i32 %d, %e
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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%4 = add i32 %3, %a
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}sgpr_if_else_salu_br_opt:
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; SI: s_cmp_lg_u32
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; SI: s_cbranch_scc0 [[IF:BB[0-9]+_[0-9]+]]
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; SI: ; %bb.1: ; %else
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; SI: s_load_dword [[LOAD0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2e
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; SI: s_load_dword [[LOAD1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x37
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; SI-NOT: add
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; SI: s_branch [[ENDIF:BB[0-9]+_[0-9]+]]
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; SI: [[IF]]: ; %if
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; SI: s_load_dword [[LOAD0]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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; SI: s_load_dword [[LOAD1]], s{{\[[0-9]+:[0-9]+\]}}, 0x25
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; SI-NOT: add
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; SI: [[ENDIF]]: ; %endif
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; SI: s_add_i32 s{{[0-9]+}}, [[LOAD0]], [[LOAD1]]
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; SI: buffer_store_dword
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; SI-NEXT: s_endpgm
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define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
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entry:
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%cmp0 = icmp eq i32 %a, 0
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br i1 %cmp0, label %if, label %else
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if:
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%add0 = add i32 %b, %c
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br label %endif
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else:
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%add1 = add i32 %d, %e
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br label %endif
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endif:
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%phi = phi i32 [%add0, %if], [%add1, %else]
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%add2 = add i32 %phi, %a
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store i32 %add2, i32 addrspace(1)* %out
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ret void
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}
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; The two S_ADD instructions should write to different registers, since
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; different threads will take different control flow paths.
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; SI-LABEL: {{^}}sgpr_if_else_valu_br:
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; SI: s_add_i32 [[SGPR:s[0-9]+]]
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; SI-NOT: s_add_i32 [[SGPR]]
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define amdgpu_kernel void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%tid_f = uitofp i32 %tid to float
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%tmp1 = fcmp ueq float %tid_f, 0.0
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br i1 %tmp1, label %if, label %else
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if:
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%tmp2 = add i32 %b, %c
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br label %endif
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else:
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%tmp3 = add i32 %d, %e
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br label %endif
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endif:
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%tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}sgpr_if_else_valu_cmp_phi_br:
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; SI: ; %else
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI: v_cmp_gt_i32_e32 vcc, 0, [[AVAL]]
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; SI: s_and_b64 [[PHI:s\[[0-9]+:[0-9]+\]]], vcc, exec
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; SI: ; %if
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI-DAG: v_cmp_eq_u32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]]
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; SI-DAG: s_andn2_b64 [[PHI]], [[PHI]], exec
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; SI-DAG: s_and_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP_ELSE]], exec
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; SI: s_or_b64 [[PHI]], [[PHI]], [[TMP]]
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; SI: ; %endif
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; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[PHI]]
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; SI: buffer_store_dword [[RESULT]],
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define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%tmp1 = icmp eq i32 %tid, 0
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br i1 %tmp1, label %if, label %else
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if:
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%gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
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%a.val = load i32, i32 addrspace(1)* %gep.if
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%cmp.if = icmp eq i32 %a.val, 0
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br label %endif
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else:
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%gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
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%b.val = load i32, i32 addrspace(1)* %gep.else
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%cmp.else = icmp slt i32 %b.val, 0
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br label %endif
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endif:
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%tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
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%ext = sext i1 %tmp4 to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { readnone }
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