forked from OSchip/llvm-project
269 lines
13 KiB
LLVM
269 lines
13 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}buffer_store:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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;CHECK: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 glc
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;CHECK: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 slc
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define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_immoffs:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:42
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define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_idx:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_ofs:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
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define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_both:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
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define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_both_reversed:
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;CHECK: v_mov_b32_e32 v6, v4
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
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define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0)
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ret void
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}
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; Ideally, the register allocator would avoid the wait here
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;
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;CHECK-LABEL: {{^}}buffer_store_wait:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
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;VERDE: s_waitcnt expcnt(0)
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;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) {
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main_body:
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call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x2:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_offen_merged:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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define amdgpu_ps void @buffer_store_x1_offen_merged(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 0, i32 %a3, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 0, i32 %a4, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 0, i32 %a5, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 0, i32 %a6, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_offen_merged_glc_slc:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}}
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}}
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}}
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define amdgpu_ps void @buffer_store_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 0, i32 %a3, i1 1, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 0, i32 %a4, i1 1, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 0, i32 %a5, i1 1, i1 1)
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call void @llvm.amdgcn.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 0, i32 %a6, i1 1, i1 1)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x2_offen_merged:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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define amdgpu_ps void @buffer_store_x2_offen_merged(<4 x i32> inreg %rsrc, i32 %a, <2 x float> %v1, <2 x float> %v2) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x3_offen_merged:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx3 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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define amdgpu_ps void @buffer_store_x3_offen_merged(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3) {
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%a1 = add i32 %a, 28
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%a2 = add i32 %a, 32
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%a3 = add i32 %a, 36
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 0, i32 %a3, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x3_offen_merged2:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx3 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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define amdgpu_ps void @buffer_store_x3_offen_merged2(<4 x i32> inreg %rsrc, i32 %a, <2 x float> %v1, float %v2) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x3_offen_merged3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx3 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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define amdgpu_ps void @buffer_store_x3_offen_merged3(<4 x i32> inreg %rsrc, i32 %a, float %v1, <2 x float> %v2) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_offset_merged:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28
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define amdgpu_ps void @buffer_store_x1_offset_merged(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 0, i32 28, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 0, i32 32, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x2_offset_merged:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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define amdgpu_ps void @buffer_store_x2_offset_merged(<4 x i32> inreg %rsrc, <2 x float> %v1, <2 x float> %v2) {
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x3_offset_merged:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx3 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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define amdgpu_ps void @buffer_store_x3_offset_merged(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3) {
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x3_offset_merged2:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx3 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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define amdgpu_ps void @buffer_store_x3_offset_merged2(<4 x i32> inreg %rsrc, float %v1, <2 x float> %v2) {
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call void @llvm.amdgcn.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x3_offset_merged3:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx3 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:8
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define amdgpu_ps void @buffer_store_x3_offset_merged3(<4 x i32> inreg %rsrc, <2 x float> %v1, float %v2) {
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call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_byte:
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;CHECK-NOT: s_waitcnt
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;CHECK-NEXT: %bb.
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;CHECK: buffer_store_byte v{{[0-9]}}, off, s[0:3], 0 offset:8
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define amdgpu_ps void @buffer_store_byte(<4 x i32> inreg %rsrc, float %v1) {
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main_body:
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%v2 = fptoui float %v1 to i32
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%v3 = trunc i32 %v2 to i8
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call void @llvm.amdgcn.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_short:
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;CHECK-NOT: s_waitcnt
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;CHECK-NEXT: %bb.
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;CHECK: buffer_store_short v{{[0-9]}}, off, s[0:3], 0 offset:16
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define amdgpu_ps void @buffer_store_short(<4 x i32> inreg %rsrc, float %v1) {
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main_body:
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%v2 = fptoui float %v1 to i32
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%v3 = trunc i32 %v2 to i16
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call void @llvm.amdgcn.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.buffer.store.i8(i8, <4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.buffer.store.i16(i16, <4 x i32>, i32, i32, i1, i1) #0
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declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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