forked from OSchip/llvm-project
185 lines
6.0 KiB
LLVM
185 lines
6.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,FUNC %s
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; FUNC-LABEL: {{^}}s_add_i32:
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; GCN: s_add_i32 s[[REG:[0-9]+]], {{s[0-9]+, s[0-9]+}}
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; GCN: v_mov_b32_e32 v[[V_REG:[0-9]+]], s[[REG]]
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; GCN: buffer_store_dword v[[V_REG]],
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define amdgpu_kernel void @s_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%a = load i32, i32 addrspace(1)* %in
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%b = load i32, i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v2i32:
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; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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define amdgpu_kernel void @s_add_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
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%result = add <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v4i32:
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; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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define amdgpu_kernel void @s_add_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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%result = add <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v8i32:
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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define amdgpu_kernel void @s_add_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
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entry:
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%0 = add <8 x i32> %a, %b
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store <8 x i32> %0, <8 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v16i32:
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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define amdgpu_kernel void @s_add_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
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entry:
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%0 = add <16 x i32> %a, %b
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store <16 x i32> %0, <16 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_add_i32:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, [[A]], [[B]]
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[A]], [[B]]
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define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1
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%a = load volatile i32, i32 addrspace(1)* %gep
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%b = load volatile i32, i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_add_imm_i32:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, 0x7b, [[A]]
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 0x7b, [[A]]
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define amdgpu_kernel void @v_add_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1
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%a = load volatile i32, i32 addrspace(1)* %gep
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%result = add i32 %a, 123
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}add64:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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define amdgpu_kernel void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%add = add i64 %a, %b
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store i64 %add, i64 addrspace(1)* %out
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ret void
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}
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; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
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; use VCC. The test is designed so that %a will be stored in an SGPR and
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; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
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; to a VGPR before doing the add.
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; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
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; GCN-NOT: v_addc_u32_e32 s
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define amdgpu_kernel void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64, i64 addrspace(1)* %in
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%1 = add i64 %a, %0
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; Test i64 add inside a branch.
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; FUNC-LABEL: {{^}}add64_in_branch:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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define amdgpu_kernel void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i64, i64 addrspace(1)* %in
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br label %endif
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else:
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%2 = add i64 %a, %b
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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; Make sure the VOP3 form of add is initially selected. Otherwise pair
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; of opies from/to VCC would be necessary
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; GCN-LABEL: {{^}}add_select_vop3:
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; SI: v_add_i32_e64 v0, s[0:1], s0, v0
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; VI: v_add_u32_e64 v0, s[0:1], s0, v0
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; GFX9: v_add_u32_e32 v0, s0, v0
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; GCN: ; def vcc
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; GCN: ds_write_b32
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; GCN: ; use vcc
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define amdgpu_ps void @add_select_vop3(i32 inreg %s, i32 %v) {
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%vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
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%sub = add i32 %v, %s
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store i32 %sub, i32 addrspace(3)* undef
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call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc)
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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