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llvm-project/llvm/lib/Target/RISCV
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Alex Bradbury 6758ecb98c [RISCV] Add support for all RV32I instructions 
This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).

Differential Revision: https://reviews.llvm.org/D23566

llvm-svn: 313485
 		2017-09-17 14:27:35 +00:00
..
AsmParser [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
InstPrinter [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
MCTargetDesc [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
TargetInfo [RISCV] Add bare-bones RISC-V MCTargetDesc 2016-11-01 23:47:30 +00:00
CMakeLists.txt [RISCV] Add RISCVInstPrinter and basic MC assembler tests 2017-08-15 13:08:29 +00:00
LLVMBuild.txt [RISCV] Add RISCVInstPrinter and basic MC assembler tests 2017-08-15 13:08:29 +00:00
RISCV.td [RISCV] Add basic RISCVAsmParser 2017-08-08 14:32:35 +00:00
RISCVInstrFormats.td [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr 2017-02-14 05:17:23 +00:00
RISCVInstrInfo.td [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
RISCVRegisterInfo.td
…
RISCVTargetMachine.cpp Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00
RISCVTargetMachine.h Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00