forked from OSchip/llvm-project
228 lines
7.6 KiB
YAML
228 lines
7.6 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: cluster_add_addc
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# GCN: S_NOP 0, implicit-def %vcc
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# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit %exec
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# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %3, implicit %exec
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name: cluster_add_addc
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
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%6 = V_MOV_B32_e32 0, implicit %exec
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%7 = V_MOV_B32_e32 0, implicit %exec
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S_NOP 0, implicit def %vcc
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%4, %5 = V_ADDC_U32_e64 %6, %7, %3, implicit %exec
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...
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# GCN-LABEL: name: interleave_add64s
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# GCN: dead %8:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit %exec
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# GCN-NEXT: dead %12:vgpr_32, dead %13:sreg_64_xexec = V_ADDC_U32_e64 %4, %5, %9, implicit %exec
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# GCN-NEXT: dead %10:vgpr_32, %11:sreg_64_xexec = V_ADD_I32_e64 %2, %3, implicit %exec
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# GCN-NEXT: dead %14:vgpr_32, dead %15:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %11, implicit %exec
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name: interleave_add64s
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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- { id: 8, class: vgpr_32 }
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- { id: 9, class: sreg_64_xexec }
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- { id: 10, class: vgpr_32 }
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- { id: 11, class: sreg_64_xexec }
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- { id: 12, class: vgpr_32 }
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- { id: 13, class: sreg_64_xexec }
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- { id: 14, class: vgpr_32 }
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- { id: 15, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%2 = V_MOV_B32_e32 0, implicit %exec
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%3 = V_MOV_B32_e32 0, implicit %exec
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%4 = V_MOV_B32_e32 0, implicit %exec
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%5 = V_MOV_B32_e32 0, implicit %exec
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%6 = V_MOV_B32_e32 0, implicit %exec
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%7 = V_MOV_B32_e32 0, implicit %exec
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%8, %9 = V_ADD_I32_e64 %0, %1, implicit %exec
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%10, %11 = V_ADD_I32_e64 %2, %3, implicit %exec
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%12, %13 = V_ADDC_U32_e64 %4, %5, %9, implicit %exec
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%14, %15 = V_ADDC_U32_e64 %6, %7, %11, implicit %exec
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...
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# GCN-LABEL: name: cluster_mov_addc
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# GCN: S_NOP 0, implicit-def %vcc
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# GCN-NEXT: %2:sreg_64_xexec = S_MOV_B64 0
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# GCN-NEXT: dead %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 %0, %1, %2, implicit %exec
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name: cluster_mov_addc
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sreg_64_xexec }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%2 = S_MOV_B64 0
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S_NOP 0, implicit def %vcc
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%3, %4 = V_ADDC_U32_e64 %0, %1, %2, implicit %exec
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...
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# GCN-LABEL: name: no_cluster_add_addc_diff_sgpr
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# GCN: dead %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit %exec
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# GCN-NEXT: %6:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
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# GCN-NEXT: %7:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
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# GCN-NEXT: S_NOP 0, implicit-def %vcc
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# GCN-NEXT: %8:sreg_64_xexec = S_MOV_B64 0
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# GCN-NEXT: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %8, implicit %exec
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name: no_cluster_add_addc_diff_sgpr
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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- { id: 8, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%8 = S_MOV_B64 0
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%2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
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%6 = V_MOV_B32_e32 0, implicit %exec
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%7 = V_MOV_B32_e32 0, implicit %exec
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S_NOP 0, implicit def %vcc
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%4, %5 = V_ADDC_U32_e64 %6, %7, %8, implicit %exec
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...
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# GCN-LABEL: name: cluster_sub_subb
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# GCN: S_NOP 0, implicit-def %vcc
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# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_SUB_I32_e64 %0, %1, implicit %exec
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# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_SUBB_U32_e64 %6, %7, %3, implicit %exec
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name: cluster_sub_subb
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%2, %3 = V_SUB_I32_e64 %0, %1, implicit %exec
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%6 = V_MOV_B32_e32 0, implicit %exec
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%7 = V_MOV_B32_e32 0, implicit %exec
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S_NOP 0, implicit def %vcc
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%4, %5 = V_SUBB_U32_e64 %6, %7, %3, implicit %exec
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...
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# GCN-LABEL: name: cluster_cmp_cndmask
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# GCN: S_NOP 0, implicit-def %vcc
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# GCN-NEXT: %3:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
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# GCN-NEXT: dead %4:vgpr_32 = V_CNDMASK_B32_e64 %0, %1, %3, implicit %exec
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name: cluster_cmp_cndmask
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%3 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
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S_NOP 0, implicit def %vcc
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%4 = V_CNDMASK_B32_e64 %0, %1, %3, implicit %exec
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...
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# GCN-LABEL: name: cluster_multi_use_cmp_cndmask
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# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
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# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
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# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
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name: cluster_multi_use_cmp_cndmask
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%2 = V_MOV_B32_e32 0, implicit %exec
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%3 = V_MOV_B32_e32 0, implicit %exec
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%4 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
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S_NOP 0, implicit def %vcc
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%5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
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%6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
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...
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# GCN-LABEL: name: cluster_multi_use_cmp_cndmask2
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# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
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# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
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# GCN-NEXT: %3:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
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# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
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name: cluster_multi_use_cmp_cndmask2
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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body: |
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bb.0:
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%0 = V_MOV_B32_e32 0, implicit %exec
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%1 = V_MOV_B32_e32 0, implicit %exec
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%4 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
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%2 = V_MOV_B32_e32 0, implicit %exec
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%5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
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%3 = V_MOV_B32_e32 0, implicit %exec
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%6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
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...
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