llvm-project/llvm/test/MC/X86
Craig Topper 2ce1a697f0 [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register.
Previously we only did this if the immediate fit in 16 bits, but
the GNU assembler seems to just truncate.

Fixes PR46952
2020-09-15 19:31:48 -07:00
..
AMX
AlignedBundling [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Inputs
3DNow.s
2011-09-06-NoNewline.s
AES-32.s
AES-64.s
AVX-32.s
AVX-64.s
AVX2-32.s
AVX2-64.s
AVX512F_512-32.s
AVX512F_512-64.s
AVX512F_SCALAR-32.s
AVX512F_SCALAR-64.s
AVXAES-32.s
AVXAES-64.s
BMI1-32.s
BMI1-64.s
BMI2-32.s
BMI2-64.s
CET-32.s
CET-64.s
CLFLUSHOPT-32.s
CLFLUSHOPT-64.s
CLFSH-32.s
CLFSH-64.s
CLWB-32.s
CLWB-64.s
CLZERO-32.s
CLZERO-64.s
F16C-32.s
F16C-64.s
FMA-32.s
FMA-64.s
FXSAVE-32.s
FXSAVE-64.s
FXSAVE64-64.s
I86-32.s
I86-64.s
I186-32.s
I186-64.s
I286-32.s
I286-64.s
I386-32.s
I386-64.s
I486-32.s
I486-64.s
INVPCID-32.s
INVPCID-64.s
LWP-32.s
LWP-64.s
MMX-32.s
MMX-64.s
PKU-32.s
PKU-64.s
POPCNT-32.s
POPCNT-64.s
PPRO-32.s
PPRO-64.s
PREFETCH-32.s
PREFETCH-64.s
RDPMC-32.s
RDPMC-64.s
RDRAND-32.s
RDRAND-64.s
RDSEED-32.s
RDSEED-64.s
RDTSCP-32.s
RDTSCP-64.s
RDWRFSGS-64.s
RTM.s
SHA-32.s
SHA-64.s
SSE-32.s
SSE-64.s
SSE2-32.s
SSE2-64.s
SSE3-32.s
SSE3-64.s
SSE4a-32.s
SSE4a-64.s
SSE41-32.s
SSE41-64.s
SSE42-32.s
SSE42-64.s
SSEMXCSR-32.s
SSEMXCSR-64.s
SSE_PREFETCH-32.s
SSE_PREFETCH-64.s
SSSE3-32.s
SSSE3-64.s
SVM-32.s
SVM-64.s
VMFUNC-32.s
VMFUNC-64.s
VTX-32.s
VTX-64.s
X86_64-pku.s
X87-32.s
X87-64.s
XOP-32.s
XOP-64.s
XSAVE-32.s
XSAVE-64.s
XSAVEC-32.s
XSAVEC-64.s
XSAVEOPT-32.s
XSAVEOPT-64.s
XSAVES-32.s
XSAVES-64.s
abs8.s
address-size.s
align-branch-32bit.s
align-branch-align.s
align-branch-basic.s
align-branch-boundary-default.s
align-branch-bundle.s
align-branch-enhanced-relaxation.s
align-branch-fused.s
align-branch-general.s
align-branch-hardcode.s
align-branch-mixed.s
align-branch-necessary.s
align-branch-negative.s
align-branch-pad-max-prefix.s
align-branch-prefix.s
align-branch-relax-all.s
align-branch-section-size.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
align-branch-section-type.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
align-branch-single.s
align-branch-system.s
align-branch-variant-symbol.s
align-via-padding-corner.s
align-via-padding.s
align-via-relaxation.s
avx512-encodings.s
avx512-err.s
avx512_bf16-encoding.s
avx512_bf16_vl-encoding.s
avx512bitalg-encoding.s
avx512bw-encoding.s
avx512gfni-encoding.s
avx512ifma-encoding.s
avx512ifmavl-encoding.s
avx512vaes-encoding.s
avx512vbmi-encoding.s
avx512vbmi2-encoding.s
avx512vbmi2vl-encoding.s
avx512vl-encoding.s
avx512vl_bitalg-encoding.s
avx512vl_gfni-encoding.s
avx512vl_vaes-encoding.s
avx512vl_vnni-encoding.s
avx512vlvpclmul.s
avx512vnni-encoding.s
avx512vp2intersectvl-att.s
avx512vp2intersectvl-intel.s
avx512vpclmul.s
avx5124fmaps-encoding.s
avx5124vnniw-encoding.s
avx_vaes-encoding.s
cet-encoding.s
cfi-open-within-another-crash.s
cfi-scope-errors.s
cfi-scope-unclosed.s
cfi_def_cfa-crash.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
check-end-of-data-region.s
code16-32-64.s
code16gcc.s [X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode. 2020-07-27 21:11:42 -07:00
compact-unwind.s
crlf.test
data-prefix-fail.s
data-prefix16.s
data-prefix32.s
data-prefix64.s
directive-arch.s [X86] Parse and ignore .arch directives 2020-07-30 08:30:06 -07:00
disassemble-zeroes.s
dwarf-size-field-overflow.test
encoder-fail.s
error-reloc.s
eval-fill.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
expand-var.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
faultmap-section-parsing.s
fde-reloc.s
fixup-cpu-mode.s
fp-setup-macho.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
gather.s
gfni-encoding.s
gnux32-dwarf-gen.s
hex-immediates.s
i386-darwin-frame-register.ll
imm-comments.s
index-operations.s
inline-asm-obj.ll
intel-syntax-2.s
intel-syntax-32.s
intel-syntax-ambiguous.s
intel-syntax-avx512-error.s
intel-syntax-avx512.s
intel-syntax-avx512_bf16.s
intel-syntax-avx512_bf16_vl.s
intel-syntax-bitwise-ops.s
intel-syntax-directional-label.s
intel-syntax-encoding.s
intel-syntax-error.s
intel-syntax-hex.s
intel-syntax-invalid-basereg.s
intel-syntax-invalid-scale.s
intel-syntax-print.ll
intel-syntax-ptr-sized.s
intel-syntax-unsized-memory.s
intel-syntax-var-offset.ll
intel-syntax-x86-64-avx.s
intel-syntax-x86-64-avx512_bf16.s
intel-syntax-x86-64-avx512_bf16_vl.s
intel-syntax-x86-64-avx512f_vl.s
intel-syntax-x86-avx512dq_vl.s
intel-syntax-x86-avx512vbmi_vl.s
intel-syntax.s
invalid-sleb.s
invalid_opcode.s
large-bss.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
line-table-sections.s
lit.local.cfg
lwp-x86_64.s
lwp.s
macho-reloc-errors-x86.s
macho-reloc-errors-x86_64.s
macho-uleb.s
mpx-encodings.s
no-elf-compact-unwind.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
padlock.s
pr22004.s
pr22028.s
pr27884.s
pr28547.s
pr32530.s
pr37425.s
pr38826.s
prefix-padding-32.s
prefix-padding-64.s
relax-insn.s
relax-offset.s
reloc-directive-elf-32.s
reloc-directive-elf-64.s
reloc-directive.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
reloc-macho.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
reloc-undef-global.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
ret.s
return-column.s
shuffle-comments.s
signed-coff-pcrel.s
space-err.s
stackmap-nops.ll
stdcall.s
tlsdesc-32.s
tlsdesc-64.s
unused_reg_var_assign.s
validate-inst-att.s
validate-inst-intel.s
variant-diagnostics.s
vpclmulqdq.s
x86-16.s [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register. 2020-09-15 19:31:48 -07:00
x86-32-avx.s
x86-32-avx512_vp2intersect-intel.s
x86-32-avx512vp2intersect-att.s
x86-32-coverage.s
x86-32-fma3.s
x86-32-ms-inline-asm.s
x86-32.s [X86] Add assembler support for .d32 and .d8 mnemonic suffixes to control displacement size. 2020-08-26 10:45:50 -07:00
x86-64-avx512_bf16-encoding.s
x86-64-avx512_bf16_vl-encoding.s
x86-64-avx512_vp2intersect-intel.s
x86-64-avx512bw.s
x86-64-avx512bw_vl.s
x86-64-avx512cd.s
x86-64-avx512cd_vl.s
x86-64-avx512dq.s
x86-64-avx512dq_vl.s
x86-64-avx512f_vl.s
x86-64-avx512pf.s
x86-64-avx512vp2intersect-att.s
x86-64-avx512vp2intersectvl-att.s
x86-64-avx512vp2intersectvl-intel.s
x86-64-avx512vpopcntdq.s
x86-64.s [X86] Add assembler support for .d32 and .d8 mnemonic suffixes to control displacement size. 2020-08-26 10:45:50 -07:00
x86-GCC-inline-asm-Y-constraints.ll
x86-branch-relaxation.s
x86-directive-nops-errors.s [X86] support .nops directive 2020-08-03 11:50:56 -07:00
x86-directive-nops.s [X86] support .nops directive 2020-08-03 11:50:56 -07:00
x86-evenDirective.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
x86-itanium.ll
x86-jcxz-loop-fixup.s
x86-target-directives.s
x86-windows-itanium-libcalls.ll
x86_64-asm-match.s
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s
x86_64-bmi-encoding.s
x86_64-directive-nops.s [X86] support .nops directive 2020-08-03 11:50:56 -07:00
x86_64-encoding.s
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-hle-encoding.s
x86_64-imm-widths.s
x86_64-rand-encoding.s
x86_64-rtm-encoding.s
x86_64-signed-reloc.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
x86_64-sse4a.s
x86_64-tbm-encoding.s
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s
x86_long_nop.s
x86_nop.s
x86_operands.s