forked from OSchip/llvm-project
50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7-unknown-none-gnueabi | FileCheck %s --check-prefixes=THUMBV7
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define { i64, i8 } @mulodi_test(i64 %l, i64 %r) unnamed_addr #0 {
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; THUMBV7-LABEL: mulodi_test:
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; THUMBV7: @ %bb.0: @ %start
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; THUMBV7-NEXT: .save {r4, r5, r6, lr}
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; THUMBV7-NEXT: push {r4, r5, r6, lr}
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; THUMBV7-NEXT: umull r12, lr, r3, r0
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; THUMBV7-NEXT: movs r6, #0
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; THUMBV7-NEXT: umull r4, r5, r1, r2
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; THUMBV7-NEXT: umull r0, r2, r0, r2
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; THUMBV7-NEXT: add r4, r12
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; THUMBV7-NEXT: adds.w r12, r2, r4
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; THUMBV7-NEXT: adc r2, r6, #0
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; THUMBV7-NEXT: cmp r3, #0
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; THUMBV7-NEXT: it ne
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; THUMBV7-NEXT: movne r3, #1
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; THUMBV7-NEXT: cmp r1, #0
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; THUMBV7-NEXT: it ne
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; THUMBV7-NEXT: movne r1, #1
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; THUMBV7-NEXT: cmp r5, #0
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; THUMBV7-NEXT: and.w r1, r1, r3
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; THUMBV7-NEXT: it ne
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; THUMBV7-NEXT: movne r5, #1
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; THUMBV7-NEXT: orrs r1, r5
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; THUMBV7-NEXT: cmp.w lr, #0
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; THUMBV7-NEXT: it ne
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; THUMBV7-NEXT: movne.w lr, #1
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; THUMBV7-NEXT: orr.w r1, r1, lr
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; THUMBV7-NEXT: orrs r2, r1
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; THUMBV7-NEXT: mov r1, r12
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; THUMBV7-NEXT: pop {r4, r5, r6, pc}
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start:
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%0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %l, i64 %r) #2
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%1 = extractvalue { i64, i1 } %0, 0
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%2 = extractvalue { i64, i1 } %0, 1
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%3 = zext i1 %2 to i8
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%4 = insertvalue { i64, i8 } undef, i64 %1, 0
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%5 = insertvalue { i64, i8 } %4, i8 %3, 1
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ret { i64, i8 } %5
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}
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; Function Attrs: nounwind readnone speculatable
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #1
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attributes #0 = { nounwind readnone uwtable }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind }
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