forked from OSchip/llvm-project
76 lines
2.1 KiB
YAML
76 lines
2.1 KiB
YAML
# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
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# Check that %11 and %20 have been coalesced.
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# CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG:[0-9]+]]
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# CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG]]
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---
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name: main
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alignment: 1
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_256 }
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- { id: 4, class: sgpr_128 }
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- { id: 5, class: sgpr_256 }
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- { id: 6, class: sgpr_128 }
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- { id: 7, class: sgpr_512 }
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- { id: 9, class: vreg_512 }
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- { id: 11, class: vreg_512 }
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- { id: 18, class: vgpr_32 }
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- { id: 20, class: vreg_512 }
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- { id: 27, class: vgpr_32 }
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liveins:
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- { reg: '$sgpr2_sgpr3', virtual-reg: '%0' }
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- { reg: '$vgpr2', virtual-reg: '%1' }
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- { reg: '$vgpr3', virtual-reg: '%2' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: $sgpr2_sgpr3, $vgpr2, $vgpr3
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%0 = COPY $sgpr2_sgpr3
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%1 = COPY $vgpr2
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%2 = COPY $vgpr3
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%3 = S_LOAD_DWORDX8_IMM %0, 0, 0, 0
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%4 = S_LOAD_DWORDX4_IMM %0, 12, 0, 0
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%5 = S_LOAD_DWORDX8_IMM %0, 16, 0, 0
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%6 = S_LOAD_DWORDX4_IMM %0, 28, 0, 0
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undef %7.sub0 = S_MOV_B32 212739
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%20 = COPY %7
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%11 = COPY %20
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%11.sub1 = COPY %1
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%11.sub2 = COPY %1
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%11.sub3 = COPY %1
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%11.sub4 = COPY %1
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%11.sub5 = COPY %1
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%11.sub6 = COPY %1
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%11.sub7 = COPY %1
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%11.sub8 = COPY %1
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dead %18 = IMAGE_SAMPLE_C_D_O_V1_V16 %11, %3, %4, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (load 4)
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%20.sub1 = COPY %2
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%20.sub2 = COPY %2
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%20.sub3 = COPY %2
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%20.sub4 = COPY %2
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%20.sub5 = COPY %2
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%20.sub6 = COPY %2
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%20.sub7 = COPY %2
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%20.sub8 = COPY %2
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dead %27 = IMAGE_SAMPLE_C_D_O_V1_V16 %20, %5, %6, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (load 4)
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...
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