forked from OSchip/llvm-project
61 lines
3.0 KiB
LLVM
61 lines
3.0 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a53 -enable-post-misched=false -enable-aa-sched-mi | FileCheck %s
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; Check that the vector store intrinsic does not prevent fmla instructions from
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; being scheduled together. Since the vector loads and stores generated from
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; the intrinsics do not alias each other, the store can be pushed past the load.
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; This allows fmla instructions to be scheduled together.
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; CHECK: fmla
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; CHECK-NEXT: fmla
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; CHECK-NEXT: fmla
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; CHECK-NEXT: fmla
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target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
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target triple = "aarch64--linux-gnu"
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%Struct = type { i64*, [9 x double], [16 x {float, float}], [16 x {float, float}], i32, i32 }
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; Function Attrs: nounwind
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define linkonce_odr void @func(%Struct* nocapture %this) unnamed_addr #0 align 2 {
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entry:
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%0 = insertelement <4 x float> undef, float undef, i32 0
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%1 = insertelement <4 x float> %0, float undef, i32 1
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%2 = insertelement <4 x float> %1, float undef, i32 2
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%3 = insertelement <4 x float> %2, float undef, i32 3
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%scevgep = getelementptr %Struct, %Struct* %this, i64 0, i32 2, i64 8, i32 0
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%struct_ptr = bitcast float* %scevgep to i8*
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%vec1 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0i8(i8* %struct_ptr)
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%ev1 = extractvalue { <4 x float>, <4 x float> } %vec1, 1
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%fm1 = fmul <4 x float> %0, %ev1
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%av1 = fadd <4 x float> %1, %fm1
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%ev2 = extractvalue { <4 x float>, <4 x float> } %vec1, 0
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%fm2 = fmul <4 x float> %2, %ev2
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%av2 = fadd <4 x float> %3, %fm2
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%scevgep2 = getelementptr %Struct, %Struct* %this, i64 0, i32 3, i64 8, i32 0
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%struct_ptr2 = bitcast float* %scevgep2 to i8*
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tail call void @llvm.aarch64.neon.st2.v4f32.p0i8(<4 x float> %av2, <4 x float> %av1, i8* %struct_ptr2)
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%scevgep3 = getelementptr %Struct, %Struct* %this, i64 0, i32 2, i64 12, i32 0
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%struct_ptr3 = bitcast float* %scevgep3 to i8*
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%vec2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0i8(i8* %struct_ptr3)
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%ev3 = extractvalue { <4 x float>, <4 x float> } %vec2, 1
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%fm3 = fmul <4 x float> %0, %ev3
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%av3 = fadd <4 x float> %1, %fm3
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%ev4 = extractvalue { <4 x float>, <4 x float> } %vec2, 0
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%fm4 = fmul <4 x float> %2, %ev4
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%av4 = fadd <4 x float> %3, %fm4
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%scevgep4 = getelementptr %Struct, %Struct* %this, i64 0, i32 3, i64 12, i32 0
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%struct_ptr4 = bitcast float* %scevgep4 to i8*
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tail call void @llvm.aarch64.neon.st2.v4f32.p0i8(<4 x float> %av4, <4 x float> %av3, i8* %struct_ptr4)
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ret void
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}
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; Function Attrs: nounwind readonly
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declare { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0i8(i8*) #2
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; Function Attrs: nounwind
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declare void @llvm.aarch64.neon.st2.v4f32.p0i8(<4 x float>, <4 x float>, i8* nocapture) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readonly }
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