forked from OSchip/llvm-project
67 lines
1.9 KiB
YAML
67 lines
1.9 KiB
YAML
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_rem() {
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entry:
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ret void
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}
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...
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---
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name: test_rem
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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- { id: 9, class: _ }
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- { id: 10, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK: [[QUOT:%[0-9]+]](s64) = G_UDIV %0, %1
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; CHECK: [[PROD:%[0-9]+]](s64) = G_MUL [[QUOT]], %1
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; CHECK: [[RES:%[0-9]+]](s64) = G_SUB %0, [[PROD]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = G_UREM %0, %1
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; CHECK: [[QUOT:%[0-9]+]](s32) = G_SDIV %3, %4
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; CHECK: [[PROD:%[0-9]+]](s32) = G_MUL [[QUOT]], %4
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; CHECK: [[RES:%[0-9]+]](s32) = G_SUB %3, [[PROD]]
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%3(s32) = G_TRUNC %0
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%4(s32) = G_TRUNC %1
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%5(s32) = G_SREM %3, %4
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; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %6
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; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %7
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; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]]
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; CHECK: [[QUOT:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
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; CHECK: [[PROD:%[0-9]+]](s8) = G_MUL [[QUOT]], %7
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; CHECK: [[RES:%[0-9]+]](s8) = G_SUB %6, [[PROD]]
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%6(s8) = G_TRUNC %0
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%7(s8) = G_TRUNC %1
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%8(s8) = G_SREM %6, %7
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; CHECK: %d0 = COPY %0
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; CHECK: %d1 = COPY %1
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; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
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; CHECK: %9(s64) = COPY %d0
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%9(s64) = G_FREM %0, %1
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; CHECK: %s0 = COPY %3
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; CHECK: %s1 = COPY %4
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; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
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; CHECK: %10(s32) = COPY %s0
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%10(s32) = G_FREM %3, %4
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...
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