forked from OSchip/llvm-project
33 lines
1.4 KiB
LLVM
33 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Effectively, check that the compile finishes; in the case
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; of an infinite loop, llc toggles between merging 2 ST4s
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; ( MergeConsecutiveStores() ) and breaking the resulting ST8
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; apart ( LegalizeStoreOps() ).
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target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
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; GCN-LABEL: {{^}}_Z6brokenPd:
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; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}
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; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}
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define amdgpu_kernel void @_Z6brokenPd(double* %arg) {
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bb:
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%tmp = alloca double, align 8, addrspace(5)
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%tmp1 = alloca double, align 8, addrspace(5)
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%tmp2 = load double, double* %arg, align 8
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br i1 1, label %bb6, label %bb4
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bb3: ; No predecessors!
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br label %bb4
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bb4: ; preds = %bb3, %bb
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%tmp5 = phi double addrspace(5)* [ %tmp1, %bb3 ], [ %tmp, %bb ]
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store double %tmp2, double addrspace(5)* %tmp5, align 8
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br label %bb6
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bb6: ; preds = %bb4, %bb
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%tmp7 = phi double [ 0x7FF8123000000000, %bb4 ], [ 0x7FF8000000000000, %bb ]
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store double %tmp7, double* %arg, align 8
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ret void
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}
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