llvm-project/llvm/test/CodeGen
Thomas Lively af7925b4dd [WebAssembly] Codegen for f64x2.convert_low_i32x4_{s,u}
Add a custom DAG combine and ISD opcode for detecting patterns like

  (uint_to_fp (extract_subvector ...))

before the extract_subvector is expanded to ensure that they will ultimately
lower to f64x2.convert_low_i32x4_{s,u} instructions. Since these instructions
are no longer prototypes and can now be produced via standard IR, this commit
also removes the target intrinsics and builtins that had been used to prototype
the instructions.

Differential Revision: https://reviews.llvm.org/D100425
2021-04-14 10:42:45 -07:00
..
AArch64 [AArch64][v8.5A] Add BTI to all function starts 2021-04-14 15:24:01 +01:00
AMDGPU [AMDGPU] Rename "LDS lowering" pass name. 2021-04-14 20:19:53 +05:30
ARC
ARM StackProtector: ensure protection does not interfere with tail call frame. 2021-04-13 15:14:57 +01:00
AVR
BPF BPF: remove default .extern data section 2021-04-13 11:35:52 -07:00
Generic [Debug-Info] make fortran CHARACTER(1) type as valid unsigned type 2021-04-11 23:17:01 -04:00
Hexagon
Inputs
Lanai
M68k
MIR [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
MSP430
Mips
NVPTX
PowerPC [AIX] Allow safe for 32bit P8 VSX pattern matching 2021-04-14 08:12:48 -04:00
RISCV [RISCV] Implement COPY for Zvlsseg registers 2021-04-13 18:55:51 -07:00
SPARC
SystemZ
Thumb
Thumb2 [ARM] Add a number of intrinsics for MVE lane interleaving 2021-04-12 17:23:02 +01:00
VE
WebAssembly [WebAssembly] Codegen for f64x2.convert_low_i32x4_{s,u} 2021-04-14 10:42:45 -07:00
WinCFGuard
WinEH
X86 [X86] Add PR49028 test case 2021-04-14 15:55:21 +01:00
XCore