..
AArch64
[AArch64] Add support for secrel add/load/store relocations for COFF
2018-03-01 20:42:28 +00:00
AMDGPU
[AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CI
2018-04-04 13:54:55 +00:00
ARM
[ARM] Do not convert some vmov instructions
2018-04-04 08:54:19 +00:00
AVR
[AVR] Implement some missing code paths
2017-12-11 11:01:27 +00:00
AsmParser
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
BPF
bpf: New disassembler testcases for 32-bit subregister support
2018-02-23 23:49:35 +00:00
COFF
[IR] Avoid the need to prefix MS C++ symbols with '\01'
2018-03-16 20:13:32 +00:00
Disassembler
[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
2018-04-02 17:09:20 +00:00
ELF
Reapply "[DWARFv5] Emit file 0 to the line table."
2018-03-29 17:16:41 +00:00
Hexagon
[Hexagon] Recognize and handle :endloop01
2018-03-30 15:29:47 +00:00
Lanai
[lanai] Add more tests for assembly of conditional ALU ops
2016-07-11 17:58:16 +00:00
MachO
[DebugInfo] Support DWARF v5 source code embedding extension
2018-02-23 23:01:06 +00:00
Mips
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
PowerPC
[PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.
2018-02-23 15:55:16 +00:00
RISCV
[RISCV] Implement MC relaxations for compressed instructions.
2018-03-02 22:04:12 +00:00
Sparc
[Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed
2017-07-25 15:28:28 +00:00
SystemZ
[SystemZ, AsmParser] Enable the mnemonic spell corrector.
2017-07-18 09:17:00 +00:00
WebAssembly
[WebAssembly] Allow for the creation of user-defined custom sections
2018-04-05 17:01:39 +00:00
X86
[X86] Added support for nocf_check attribute for indirect Branch Tracking
2018-03-17 13:29:46 +00:00