llvm-project/llvm/test/CodeGen
Aditya Nandakumar e6201c8724 [GISel]: Rework legalization algorithm for better elimination of
artifacts along with DCE

Legalization Artifacts are all those insts that are there to make the
type system happy. Currently, the target needs to say all combinations
of extends and truncs are legal and there's no way of verifying that
post legalization, we only have *truly* legal instructions. This patch
changes roughly the legalization algorithm to process all illegal insts
at one go, and then process all truncs/extends that were added to
satisfy the type constraints separately trying to combine trivial cases
until they converge. This has the added benefit that, the target
legalizerinfo can only say which truncs and extends are okay and the
artifact combiner would combine away other exts and truncs.

Updated legalization algorithm to roughly the following pseudo code.

WorkList Insts, Artifacts;
collect_all_insts_and_artifacts(Insts, Artifacts);

do {
  for (Inst in Insts)
         legalizeInstrStep(Inst, Insts, Artifacts);
  for (Artifact in Artifacts)
         tryCombineArtifact(Artifact, Insts, Artifacts);
} while(!Insts.empty());

Also, wrote a simple wrapper equivalent to SetVector, except for
erasing, it avoids moving all elements over by one and instead just
nulls them out.

llvm-svn: 318210
2017-11-14 22:42:19 +00:00
..
AArch64 [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
AMDGPU [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
ARC
ARM [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
AVR [AVR] Remove the select-mbb-placement-bug.ll test 2017-11-14 04:32:49 +00:00
BPF bpf: fix bug on silently truncating 64-bit immediate 2017-10-16 04:14:53 +00:00
Generic [CodeGen] Peel off the dominant case in switch statement in lowering 2017-11-14 21:44:09 +00:00
Hexagon [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rr 2017-11-02 21:56:59 +00:00
Inputs
Lanai MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
MIR [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
MSP430
Mips [mips] Simplify test for 5.0.1 (NFC) 2017-11-14 19:11:45 +00:00
NVPTX [NVPTX] Implement __nvvm_atom_add_gen_d builtin. 2017-11-07 22:10:54 +00:00
Nios2
PowerPC Rename CountingFunctionInserter and use for both mcount and cygprofile calls, before and after inlining 2017-11-14 21:09:45 +00:00
RISCV [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py 2017-11-09 15:45:42 +00:00
SPARC Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" 2017-10-03 16:59:13 +00:00
SystemZ [CodeGen] Peel off the dominant case in switch statement in lowering 2017-11-14 21:44:09 +00:00
Thumb [ARM] Fix incorrect conversion of a tail call to an ordinary call 2017-11-14 10:36:52 +00:00
Thumb2 [arm] Fix Unnecessary reloads from GOT. 2017-11-13 20:45:38 +00:00
WebAssembly Use input redirection in WebAssembly/comdat.ll test. 2017-11-14 14:26:42 +00:00
WinEH Make x86 __ehhandler comdat if parent function is 2017-10-20 17:04:43 +00:00
X86 [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
XCore [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00