forked from OSchip/llvm-project
103 lines
4.2 KiB
C++
103 lines
4.2 KiB
C++
//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsSEISELLOWERING_H
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#define MipsSEISELLOWERING_H
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#include "MipsISelLowering.h"
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#include "MipsRegisterInfo.h"
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namespace llvm {
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class MipsSETargetLowering : public MipsTargetLowering {
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public:
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explicit MipsSETargetLowering(MipsTargetMachine &TM);
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/// \brief Enable MSA support for the given integer type and Register
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/// class.
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void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
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/// \brief Enable MSA support for the given floating-point type and
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/// Register class.
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void addMSAFloatType(MVT::SimpleValueType Ty,
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const TargetRegisterClass *RC);
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
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virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
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EVT VT) const {
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return false;
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}
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virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
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if (VT == MVT::Untyped)
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return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
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&Mips::ACC64RegClass;
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return TargetLowering::getRepRegClassFor(VT);
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}
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private:
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virtual bool
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isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const;
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virtual void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
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/// depending on the indices in the shuffle.
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SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned BranchOp) const;
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/// \brief Emit the COPY_FW pseudo instruction
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MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the COPY_FD pseudo instruction
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MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the INSERT_FW pseudo instruction
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MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the INSERT_FD pseudo instruction
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MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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}
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#endif // MipsSEISELLOWERING_H
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